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The flexible architecture of TrekSoC enables it to be integrated into multiple type of verification environments.

Full-Chip RTL Testbench

A full-chip verification environment is one that contains the processor models and runs C test code. TrekSoC generates C test cases that are compiled and run on the embedded processors.


Full-Chip Environment Integration

TrekBox is a System Verilog module, provided by Breker, which is instantiated at the top level of the SoC testbench and becomes active when running TrekSoC test cases. The TrekBox module is provided with a hierarchical RTL path to an address in system memory that will be used as a mailbox.

When TrekSoC generates a C test case, it also generates an events file for consumption by TrekBox. This events file contains the testbench operations, such as the manipulation of external input signals, which are required for running the C test. Each required event is given a unique event id. When threads in the C test case reach predetermined execution points an event id is sent to TrekBox to trigger the required testbench operation. These actions are performed through the DPI interface. Events only flow from the C test to TrekBox.

In simulation, TrekBox is used to manage debug tracing, driving and checking testbench BFMs, and using backdoor memory accesses for offloading results data, saving simulated processor cycles. Debug messages and expected results are stored in the events file to reduce consumption of system memory.

Transaction-Level/IP Component RTL Testbench


Transaction-Level and IP Environment Integration

In this type of verification environment, each processors is replaced by a bus functional model (BFM), or the IP blocks are directly driven by transactions. This may be done to improve simulation speed or to provide additional test control or observability.

In this configuration TrekSoC dynamically creates transactions for the processor and other BFMs. This provides better debug observability since the dynamic state of the system is known at the time of a failure. In this mode, test generation may be reactive to system state.

The same scenario models are shared between the full-chip and transaction-level environments.

The dynamic flow can also be used to reproduce failing test cases in an IP component testbench.

Test Case Generation

TrekSoC provides options to control test case generation depending on the type of simulation environment. Processor sequences can be generated as a C test case or as transactions driven through a BFM.

In the case of C tests, testbench operations are performed by TrekBox using the event id mechanism. The event id mechanism itself may be customized for each platform.