June 5-9, 2016
Breker’s Trek family of products and apps automatically generates multi-threaded test cases that verify your chip design more quickly and more thoroughly. These test cases are reusable from IP to full-chip level, and from simulation to silicon, meeting all requirements for the upcoming Accellera standard on Portable Stimulus.
- TrekUVM enhances transactional Universal Verification Methodology (UVM) testbenches for your networking, processor, and GPU chips.
- TrekSoC links UVM testbenches to generated C test cases running in simulation or acceleration on multiple heterogeneous embedded processors within your system-on-chip (SoC).
- From the same inputs, TrekSoC-Si generates test cases that run on in-circuit emulation (ICE), FPGA prototypes, and actual silicon in your lab.
- Our Cache Coherency TrekApp is a stand-alone turnkey solution for cache coherency verification from simulation to silicon.