Technology
TrekSoC automatically generates self-verifying C test cases to run on the embedded processors in SoCs. TrekSoC is built on several key technologies, including the Trek solver, the TrekSoC services used to help build scenario models, and a versatile framework that allows TrekSoC to be integrated into multiple types of verification environments. If you would like to learn more about any of these technologies, click on the appropriate link or use the pull-down menu.
The following Breker-authored papers, articles and conference talks provide more information on different aspects of the technology used in TrekSoc.
EE Times Asia: Stitch and Ship no longer Viable
Scenario models define a series of paths to exercise all possible intended behaviours, or use cases, for the SoC. This representation directly enables automated generation of test cases to run these use cases. A tool such as TrekSoC from Breker Verification Systems can "walk" the graph, analyse all possible paths and parallelism, and generate the C code necessary to run on the embedded processors and execute every individual scenario. Read more
EDA DesignLine: Why Stitch and Ship Is no longer Workable
TMost electronic design automation (EDA) vendors still continue making tools that focus on the block-level RTL verification problem and have not introduced tools that tackle system-level verification. In contrast, scenario models enable a full solution for the system-level verification problem. Read more
Verification Futures India: Generation and Visualization of Multi-Threaded Multi-Core Test Cases
Today's SoC projects are facing a verification challenge. Engineers are finding it hard to develop an effective full-chip testbench using the existing methodologies. The primary alternative, hand-writing C tests to run on the SoC's embedded processors, is time-consuming and limited because humans can't visualize multi-processor tests running in parallel. Read more
Gabe on EDA: System Prototyping and Verification Reuse
What's needed is a verification technique that fosters reuse through all three stages of system prototyping as well as simulation, acceleration and emulation. Automatic generation of self-verifying C test cases from graph-based scenario models is just such a technique. Read more
Electronic Design: Sizing Up The Verification Problem
A principal difference in this methodology is that it does not depend on the testbench being complete before verification can start. It also ensures that the most important aspects of a system are verified first. In many cases, system verification could be performed even before the blocks have been implemented and act to ensure that the specifications for those blocks are correct. Read more
Electronic Engineering Journal: Emulation Urge? Don't Give Up on Simulation Yet!
What if there was a way to automatically create a set of SoC-level tests that runs on the embedded processors and exercises all the complex operating modes of the chip, yet is sufficiently targeted to run efficiently using simulation? That is the promise of a new set of functional verification tools, including Breker's TrekSoC product, that automatically generate self-verifying C test cases for the thorough and quick verification of SoCs. Read more
Electronic Engineering Times India: Why Design Reuse sans Verification Reuse is Futile
The objective of system-level verification is not to verify the implementation of IP blocks. It is to verify that the system is capable of supporting the high-level requirements and delivering the necessary functionality and performance. Read more
EDA DesignLine: Design Reuse without Verification Reuse Is Useless
While platform design IP has increased the efficiency of the design process, VIP has failed to deliver similar gains. A new method of describing VIP, scenario models, is suitable for platform IP. It is reusable and extensible with built in notions of coverage and verification planning. Read more
Verification Futures: Close Your Coverage Loop with Graph-Based Scenario Models
Many SoC teams today just stitch and ship, focusing on connectivity tests and minimal sanity tests in the full-chip testbench. Some teams may also hand-write a few tests to run on an embedded processor, but these tend to be very simple. The result is inadequate coverage of SoC functionality at the full-chip level. Read more
Verification Futures: Break Your SoC with Automatically Generated C Test Cases
TrekSoC automatically generates self-verifying C test cases from the scenario models. These test cases are well commented so that the user can follow them running multiple threads across multiple processors within the SoC. These test cases are carefully crafted to stress the SoC, generating worst-case but legal scenarios and exploring the deep corner cases in the design. Read more
Low-Power Design: Five Verification Steps to Low-Power Success
By popular definition, every SoC contains one or more embedded processors. Running C tests on these processors in simulation can provide a more efficient way to exercise both regular functionality and low-power operation than trying to control the chip from an external testbench alone. However, hand writing such tests is difficult and time consuming. A better approach is to use a tool such as Breker's TrekSoC that automatically generates self-verifying C test cases from a set of intuitive, graph-based scenario models. Read more
Electronic Design: What's the Deal with SoC Verification?
To be fully effective, SoC verification must include automation of the tests running on the embedded processors. Software can generate multi-threaded test cases running on multiple embedded processors in simulation. The test cases stimulate and coordinate concurrent activities within the processors and within the testbench, stress-testing the SoC. The test cases must be self-verifying by generating randomized input data, calculating expected results from the inputs, and checking that the chip's outputs in simulation match the expected results. Read more
SoCcentral: Use the Power of Your SOC to Verify Its Low-Power Design Features
Given the near ubiquity of power-related structures in SOC designs, verification before tape-out is critical. Rather than relying on un-scalable testbenches, it's better to leverage the power of the SOC itself--its embedded processors--to verify low-power designs. Read more
Electronic Engineering Times Asia: Overcoming Challenges for SoC Verification Team
The TrekBox and an accompanying events file ensure that test cases running on the embedded processors are synchronized with the testbench components. This ensures that data is read into the chip at the right time and that outgoing data is checked for correctness at the right time. Read more
EDA DesignLine: The Forgotten SoC Verification Team
Bringing the integration verification earlier in the development process allows tasks such as performance verification to have a larger impact. It becomes possible to optimize the system for the desired performance and to ensure that the correct controls exist within each block for proper power management. Read more
Chip Design: Verifying SoCs from the Inside Out
Since embedded processors are the heart of the SoC, it makes sense to leverage their power and make them the heart of verification as well. This is verification from the inside out, a much better way to exercise the SoC more thoroughly and stress corner-case conditions that only exist at the full-chip level. Read more
Electronic Engineering Times: 3-D IC Implications for Verification
The difficulty of developing an effective SoC-level testbench and the lack of a methodology to coordinate with the code running on the embedded processors mean that verification teams stop short. This situation is not going to get any easier for verification of 3D ICs. The total system-level design will be even larger and more complex. Read more
GSA Forum: Solving Verification Issues Facing Semiconductor Companies Pressured to Get Products to Market
Verification engineers play an integral role in an electronic product's success since they are responsible for integration verification, performing system verification and validation. They need the right tools and methodology to be successful. Semiconductor companies can arm their verification team with a new weapon to fight the SoC verification battle that will help them succeed in the consumer market and successfully battle low margins, fierce competition and aggressive pricing. Read more
Electronic Engineering Times: Lifting the System-Level Fog with SoC Verification
What's left to do is to create a new subcategory called "SoC Verification" to highlight the special verification challenges posed by SoCs with embedded processors. Tools in this category, such as Breker's TrekSoC, take a fundamentally different approach to verification by automating self-verifying embedded C test generation, intimately linking hardware and software together. Read more
Electronic Engineering Journal: Verifying Today's SoCs Requires a New Approach
The size, complexity, and large number of shared resources in a contemporary SoC demand a new and innovative approach to verification. Leveraging scenario models to automatically generate self-verifying C test cases with connections to the testbench exercises both regular production operation and corner cases. Read more
EDA DesignLine: SoC Low-Power Verification Requires a Full-Chip Solution
The technique that has the highest impact on verification is perhaps the most widely used: power shut off (PSO). While simple in concept, PSO has many tricky aspects in implementation that must be carefully verified. Read more
Gabe on EDA: The Truth about SoC Verification
The truth about SoC verification: The SoC cannot be fully verified without running thorough automated self-verifying test cases on its embedded processors. Read more
Real Talk Blog: Avoiding the Titanic-Sized Iceberg of Downton Abbey
Automated self-verifying C test cases running on embedded processors exercise a range of functional scenarios to ensure that the SoC can support concurrency, system-level and software functionality while meeting performance requirements. Read more
Chip Design: Now Is the Time to Fix Coverage Metrics
By defining what exactly is meant by functional intent coverage, designers can make tests efficient. After all, each test exercises a specific combination of outcomes. At the same time, designers can retain the benefits of an automated approach, which allows computers to work on the verification problem instead of human beings. Read more
EDA DesignLine: Host Bus Adapter (HBA) Verification with Trek
The value of Trek is that it can generate deep state scenario from the Coverage Model and guarantee coverage closure. Read more
Chip Design:Three Views on Verification Challenges
Verification engineers now have the ability to cheaply synthesize high quality, targeted test cases that augment their existing verification flows. As a result, they can make efficient use of available simulation capacity to achieve coverage closure. Read more
