Videos « Breker Verification Systems

February 26 - March 1, 2018
Booth # 304
Double Tree Hotel, San Jose, CA

The following videos show Breker technologists and customers discussing numerous aspects of our company, products, and technology.

March 8, 2016
EDACafe: Tom Anderson Discusses Portable Stimulus at DVCon

"We've been at this longer than anyone; we've been about eight years in this space. We started originally consulting and then developed products. We have a large list of customers, so there's not a lot of new technology announcements this year but there are a number of new customers including Cavium and Altera." Read More

August 25, 2015
DVCon India: Tom Anderson, Promotion Co-chair, DVCon India 2015

You'll hear the latest ideas and thoughts on what portable stimulus means: the ability to have a test case than can be ported from an IP block to a full SoC level in simulation, and then all the way from hardware platforms into actual silicon devices with embedded processors. Read More

July 16, 2015
GSA IP Working Group: IP-Centric SoC Verification Presentation

Graphs are a way to represent the design and the intended verification space of the design. Graphs are very nice because they can be composed together. Read More

July 16, 2015
GSA IP Working Group: IP Verification Panel

At the SoC level, where you're now talking about interactions among blocks from multiple vendors, use-case coverage, scenarion coverage, terms like that are emerging. It's no clear how much the IP providers can do to help that. Read More

March 12, 2015
EDACafe: Tom Anderson Discusses How Apps Are Changing EDA

This notion of "apps" has really transformed the EDA industry. Even the large players talk about apps quite a bit. I think it was really formal and PCB boards, a couple of areas of tools that pioneered the whole app idea. Read More

March 18, 2014
EDACafe: Interview with Tom Anderson, V.P. of Marketing at Breker Verification

Every company out there that does chips has somebody hand-writing bring-up diagnostics for their chips. When you bring the chip in from the fab on the first day, it's not going to boot up Linux, it's not going to run applications. There are going to be issues, and it's much easier to debug those with focused tests. We replace those hand-written tests with a set of automated tests. Read More

June 14, 2013
EDACafé: Interview with Tom Anderson at Breker Verification Systems

The expansion of the product line is likely to happen going forward over the next 6 to 12 months. We have several new directions that we think we can take the current technology and address different aspects of the SoC verification problem beyond what we address today. Read More

MARCH 7, 2013
EDACafe: Interview with Tom Anderson, Breker V.P. of Marketing

It's really a way of verifying the SoC from the inside out. People think of testbenches primarily for verification, where you're trying to verify the chip from the outside in. You're trying to engage deep behaviors in the chip purely through the I/O ports. That's hard to do on a big chip. Read More

February 27, 2013
YouTube: Verifying Complex Chips

People are discovering that a pure testbench approach is not sufficient when you're trying to verify the whole SoC together. UVM is great as far as it goes; it works great on IP but it really doesn't scale to the full-chip level. Read More

November 28, 2012
YouTube: The Growing Verification Challenge

Systems get verified; bugs in chips just slow down time to market. The solution the world needs is, just as we've learned to plug and play IPs to build systems and plug and play software to run software on the systems, we need a way to plug and play tests that can go from the IPs to the systems to the software. Read More

September 1, 2011
YouTube: A Trek Testimonial

[Trek] enhances productivity at each level of verification for us. Read More

MARCH 2, 2011
EDACafe: Trek Functional Scenario Verification

We allow our users a concise way of describing the functional scenarios that need to be tested on the design. From this description we can synthesize inputs for UVM components, grab the outputs from UVM components, and check to make sure that the right behavior was observed. We can measure coverage on scenarios to make sure that all the use models have been exercised. Read More