Technical Articles « Breker Verification Systems
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The following Breker-authored papers, articles and conference talks provide more information on different aspects of the technology used in our Trek family of products.

May 3, 2017
Embedded Computing Design: It's Time For An Embedded Systems Design Verification Revolution

A revolution is building right now in the verification space. Remember when everyone graduated from college and wanted to be a design engineer? Those who were not good enough got moved onto verification. Those days are over and some are suggesting that today being a verification engineer carries as much, and in some cases more, prestige. Verification tools are now about to take a page out of the design flow playbook. Who knows where this will lead the industry. Read More

March 9, 2017
EDN: The Verification Revolution

The Accellera Portable Stimulus (PS) standard is expected to be released early this year and that will set the stage for the abstraction of verification to be raised to the system level. While attempts have been made to raise the abstraction used for design, the industry decided to stay at the Register Transfer Level (RTL) for most blocks and instead use a block assembly approach to create systems using internally developed IP or IP coming from third parties. However, verification costs have been rising, and existing verification languages, such as SystemVerilog, and methodologies, including the Universal Verification Methodology (UVM) fail to address issues associated with system-level verification. Thus, the stage was set for the development of a new system level verification methodology. Read More

August 29, 2016
Electronic Design: 6 Industry Trends Reflected in Third DVCon India Technical Program

Accellera has recognized the need for an industry standard input format (Fig. 2), and the Portable Stimulus Working Group (PSWG) has been working to develop such a standard. This year’s DVCon India will include a tutorial on portable stimulus from key members of the PSWG, as well as coverage in other sessions. Furthermore, all of the vendors offering tools in this space will have booths in the DVCon India exhibition. Portable stimulus was a hot topic at both the 2014 and 2015 events, and appears likely to be so again. Read More

August 26, 2016
Chip Design: Third DVCon India Ready for Liftoff

Breker is proud to be a supporter of DVCon India for the third time. We will present a joint tutorial on portable stimulus with other members of the Accellera Portable Stimulus Working Group (PSWG) and we will have a booth in the exhibition area.   Read More

August 24, 2016
Embedded Computing Design: Hardware and Software Grow Ever Closer

While hardware and software development are likely to remain separate disciplines for many engineers, their teams are working more closely than ever. The demand for earlier production software verification, software-driven tests for SoC verification and validation, and portability across verification platforms are all driving evolution in the same direction. Read More

September 10, 2015
DVCon India: Leveraging Portable Stimulus across Domains and Disciplines

Graphs enable portable stimulus. A graph-based scenario model provides an abstract view of the design and the verification space, ... built-in coverage metrics, automatic coverage closure (nodes, arcs, etc.), vertical portability with automatic test generation for transactions and embedded C/C++, and horizontal portability, with automatic test generation from simulation to silicon. Read More

September 3, 2015
Electronic Design: 5 Industry Trends Dominate DVCon India’s Technical Program

Over the next few years, much energy will be devoted to address these five trends: UVM extensions, ESL development, many-core designs, portable stimulus, and IoT products. Engineers involved in any of these areas will want to benefit from all available information from the trade press, technical journals, and industry conferences. Read More

September 2, 2015
Embedded Computing Design: The Ongoing Merger of Embedded and EDA

It is unclear whether the embedded and EDA worlds will completely merge, served by a single set of vendors and viewed as a single market. However, the arguments that the merger will continue to happen incrementally are strong, and supported by specific examples of changes in the industry. Read More

April 20, 2015
DVClub Europe: Cache Coherency Verification with Vertical and Horizontal Portable Stimulus

Most cache coherency verification occurs with generated C test cases that run on embedded processors at every phase of the project, from ESL models through actual silicon. These test cases can be tuned for each platform, enabling true horizontal verification reuse. For IP blocks and subsystems that do not include the processors, test cases can be generated in the form of transactions for bus models within a UVM simulation testbench. This enables true vertical reuse as well. Read More

December 8, 2014
Electronic Design: Complex Chip Designs Need System-Level Scenario Coverage

Coverage metrics have long been used to help verification teams understand how well they verify chip designs. Code coverage, functional coverage, assertion coverage, and formal coverage have all shown their value. System-level coverage derived automatically from graph-based scenario models is an essential complement to traditional metrics for complex chip and SoC designs. Read More

December 3, 2014
Electronic Engineering Times: Fast, Thorough Verification of Multiprocessor SoC Cache Coherency

It is possible with current technology to generate C test cases automatically to run on the CPUs, DSP, and GPU, as well as to program the I/O controllers to read and write memory. The technology can coordinate activity in the testbench so that data can be sent into the I/O channels or readout and compared with expected values. Having all agents read and write from multiple memories and multiple levels of caches is an excellent stress test for the caching algorithms and other aspects of the design. Read More

October 10, 2014
EECatalog: SoC Verification: A Life-or-Death Issue for Medical Electronics

Elimination of corner-case bugs can be a life-or-death issue for medical electronics. An inaccurate reading from a medical instrument may lead to misdiagnosis and mistreatment during a critical period for the patient. The possibility of an implanted medical device hanging, resetting, or doing the wrong thing is even more frightening. Read More

August 27, 2014
Electronic Design: Automatically Generated C Test Cases Earn a Solid Return on Investment

Leading SoC teams today are automatically generating multi-threaded, multi-processor, self-verifying C test cases that stress the design much more thoroughly than manual methods. The minimal investment is compensated many times over by better productivity, a shorter verification schedule, and increased design quality. Read More

June 29, 2014
Global Semiconductor Alliance Forum: Unverified but Wearable Is Unbearable

Page 23: SoC verification is a challenge for today's smartphones and other devices. The expectation of perfection will be even greater for wearable technology likely to be viewed as an extension of its human user. Read More

May 27, 2014
Embedded Computing Design: Managing SoC Complexity with Scenario Model Verification

Perhaps the greatest value of a graph-scenario model is that it can be used to generate C test cases to run on embedded processors in simulation, In-Circuit Emulation (ICE), Field Programmable Gate Array (FPGA) prototypes, or the SoC silicon in the bring-up lab. A generator walks through the graph from left to right, from desired results to inputs, assembling a series of steps that work back to the set of input values required to produce a particular outcome. Graph decision points and data values are randomized so that each walkthrough produces a unique test case. Read More

April 17, 2014
Electronic Design: The Fundamentals Of Thread Visualization For Test Case Understanding And Debug

How in the world is it possible to debug an automatically generated multi-threaded, multi-processor test case? If it uncovers a lurking design bug, the verification team has to understand what the test case is doing to track down the source of the bug. A test case failure might instead be due to a mistake in the scenario model, so it must be possible to correlate the test case back to the graph where the design intent was captured. A unique visualization approach for the generated test cases provides the answer. Read More

January 13, 2014
DVClub Europe: Mapping System Coverage Metrics to Traditional Coverage Models

We are focused on the automatic generation of system-level SoC test cases for SoC designs. The strategy is to generate these C tests from something that we're calling a scenario model, and really that scenario model is all about coming up with a coverage model for the system. It turns out that you can take that graph-based model and map it to UCIS without much fuss. Read More

January 10, 2014
Electronic Design: The Verification Flow Can Enable Horizontal Reuse

It is now possible to think about what horizontal reuse means in the context of functional verification. The verification flow, from product inception through actual silicon, must be driven from a single description that should be a combination of the separated piece-meal models used today, including scoreboard, coverage model, constraints, checkers, assertions, and sequences. Read More

November 25, 2013
SOCcentral: Threading the Way through SOC Verification

Multi-threaded test cases automatically generated from scenario models are effective at finding not just bugs in the hardware design, but also in testbench models and any driver software libraries used to help construct the scenario models. Read More

November 20, 2013
Electronic Design: Remove The Processor Dilemma From Constrained-Random Verification

Embedded processors have become a central aspect of a modern SoC, and their inclusion is necessary to perform some aspects of verification not covered by old methodologies. Power and performance cannot be verified without the processors and it is not possible to extract them from real silicon, a function that would be necessary to extend the traditional verification methodology beyond the simulator. Read More

October 15, 2013
Embedded Computing Design: Hitting the wall in FPGA SoC verification

To address the diagnostic software code dilemma, FPGA SoC developers must take another page from the book of ASIC and custom chip verification. They can benefit from a method that automatically generates multithreaded, multiprocessor, self-verifying C tests that stress system-level behavior in the SoC. Read More

October 7, 2013
Tech Design Forum: Think like designers to fill the SoC verification gap

Automatically generated code can orchestrate complex usage scenarios that would be difficult to create manually. As part of this generation process, it also can add randomization so that the corner cases not specifically considered, but permitted by the graph, can be verified. Read More

September 12, 2013
Electronic Design: One Verification Model To Drive Them All

One model can be used to encapsulate an SoC design’s functionality, stimulus, results checking (possibly including assertions), coverage, and constraints. It can scale to the complexity of the system for which generation needs to happen and for the abstraction of the design being verified. Read More

September 11, 2013
GSA Forum: More than Moore and the Verification Moor

The SOC team that moves to multiple processors in an attempt to achieve a "More than Moore" speedup, quickly runs into a "moor" problem: the vast, boggy landscape of SOC verification. The simple fact is that most verification techniques and methodologies were developed for use on intellectual property (IP) blocks and smaller chips. Adding a processor to create an SOC changes the game, and adding multiple processors renders IP-class verification helpless. Read More

August 15, 2013
Electronic Engineering Journal: Avoiding the SoC Verification Iceberg

The verification iceberg accurately describes the scope of tests that must be generated in order to thoroughly verify an SoC. Neither traditional testbenches nor hand-written tests for the embedded processors can come close to covering the iceberg. The only way to avoid its risks is to automatically generate test cases from scenario models. Read More

MAY 28, 2013
Electronic Design: Surveying The Verification Landscape

If SoC functionality is represented as a graph-­based scenario model, verification goals are shown on the left with design inputs on the right. Constrained-­random stimulus starts at the right and attempts to reach interesting verification states with no guarantee of success. In contrast, a graph-­based constraint solver can select a verification goal, determine exactly the path needed to achieve that goal, and generate the appropriate software test case to execute on the embedded processors. Read More

May 9, 2013
EE Times Asia: Why Stitch and Ship Is no longer Workable

Scenario models define a series of paths to exercise all possible intended behaviours, or use cases, for the SoC. This representation directly enables automated generation of test cases to run these use cases. A tool such as TrekSoC from Breker Verification Systems can “walk” the graph, analyse all possible paths and parallelism, and generate the C code necessary to run on the embedded processors and execute every individual scenario. Read More

April 15, 2013
EDA DesignLine: Stitch and Ship no longer Viable

Most electronic design automation (EDA) vendors still continue making tools that focus on the block-level RTL verification problem and have not introduced tools that tackle system-level verification. In contrast, scenario models enable a full solution for the system-level verification problem. Read More

March 19, 2013
Verification Futures India: Generation and Visualization of Multi-Threaded Multi-Core Test Cases

Today’s SoC projects are facing a verification challenge. Engineers are finding it hard to develop an effective full-chip testbench using the existing methodologies. The primary alternative, hand-writing C tests to run on the SoC’s embedded processors, is time-consuming and limited because humans can’t visualize multi-processor tests running in parallel. Read More

January 25, 2013
Gabe on EDA: System Prototyping and Verification Reuse

What’s needed is a verification technique that fosters reuse through all three stages of system prototyping as well as simulation, acceleration and emulation. Automatic generation of self-verifying C test cases from graph-based scenario models is just such a technique. Read More

January 23, 2013
Electronic Design: Sizing Up The Verification Problem

A principal difference in this methodology is that it does not depend on the testbench being complete before verification can start. It also ensures that the most important aspects of a system are verified first. In many cases, system verification could be performed even before the blocks have been implemented and act to ensure that the specifications for those blocks are correct. Read More

January 17, 2013
Electronic Engineering Journal: Emulation Urge? Don’t Give Up on Simulation Yet!

What if there was a way to automatically create a set of SoC-level tests that runs on the embedded processors and exercises all the complex operating modes of the chip, yet is sufficiently targeted to run efficiently using simulation? That is the promise of a new set of functional verification tools, including Breker’s TrekSoC product, that automatically generate self-verifying C test cases for the thorough and quick verification of SoCs. Read More

December 14, 2012
Electronic Engineering Times India: Why Design Reuse sans Verification Reuse is Futile

The objective of system-level verification is not to verify the implementation of IP blocks. It is to verify that the system is capable of supporting the high-level requirements and delivering the necessary functionality and performance. Read More

November 26, 2012
EDA DesignLine: Design Reuse without Verification Reuse Is Useless

While platform design IP has increased the efficiency of the design process, VIP has failed to deliver similar gains. A new method of describing VIP, scenario models, is suitable for platform IP. It is reusable and extensible with built in notions of coverage and verification planning. Read More

November 22, 2012
Verification Futures: Close Your Coverage Loop with Graph-Based Scenario Models

Many SoC teams today just stitch and ship, focusing on connectivity tests and minimal sanity tests in the full-chip testbench. Some teams may also hand-write a few tests to run on an embedded processor, but these tend to be very simple. The result is inadequate coverage of SoC functionality at the full-chip level. Read More

November 21, 2012
Verification Futures: Break Your SoC with Automatically Generated C Test Cases

TrekSoC automatically generates self-verifying C test cases from the scenario models. These test cases are well commented so that the user can follow them running multiple threads across multiple processors within the SoC. These test cases are carefully crafted to stress the SoC, generating worst-case but legal scenarios and exploring the deep corner cases in the design. Read More

October 30, 2012
Low-Power Design: Five Verification Steps to Low-Power Success

By popular definition, every SoC contains one or more embedded processors. Running C tests on these processors in simulation can provide a more efficient way to exercise both regular functionality and low-power operation than trying to control the chip from an external testbench alone. However, hand writing such tests is difficult and time consuming. A better approach is to use a tool such as Breker’s TrekSoC that automatically generates self-verifying C test cases from a set of intuitive, graph-based scenario models. Read More

October 10, 2012
Electronic Design: What’s the Deal with SoC Verification?

To be fully effective, SoC verification must include automation of the tests running on the embedded processors. Software can generate multi-threaded test cases running on multiple embedded processors in simulation. The test cases stimulate and coordinate concurrent activities within the processors and within the testbench, stress-testing the SoC. The test cases must be self-verifying by generating randomized input data, calculating expected results from the inputs, and checking that the chip’s outputs in simulation match the expected results. Read More

September 1, 2012
SoCcentral: Use the Power of Your SOC to Verify Its Low-Power Design Features

Given the near ubiquity of power-related structures in SOC designs, verification before tape-out is critical. Rather than relying on un-scalable testbenches, it’s better to leverage the power of the SOC itself–its embedded processors–to verify low-power designs. Read More

August 30, 2012
Electronic Engineering Times Asia: Overcoming Challenges for SoC Verification Team

The TrekBox and an accompanying events file ensure that test cases running on the embedded processors are synchronized with the testbench components. This ensures that data is read into the chip at the right time and that outgoing data is checked for correctness at the right time. Read More

August 13, 2012
EDA DesignLine: The Forgotten SoC Verification Team

Bringing the integration verification earlier in the development process allows tasks such as performance verification to have a larger impact. It becomes possible to optimize the system for the desired performance and to ensure that the correct controls exist within each block for proper power management. Read More

August 3, 2012
Chip Design: Verifying SoCs from the Inside Out

Since embedded processors are the heart of the SoC, it makes sense to leverage their power and make them the heart of verification as well. This is verification from the inside out, a much better way to exercise the SoC more thoroughly and stress corner-case conditions that only exist at the full-chip level. Read More

JULY 16, 2012
Electronic Engineering Times: 3-D IC Implications for Verification

The difficulty of developing an effective SoC-level testbench and the lack of a methodology to coordinate with the code running on the embedded processors mean that verification teams stop short. This situation is not going to get any easier for verification of 3D ICs. The total system-level design will be even larger and more complex. Read More

June 1, 2012
GSA Forum: Solving Verification Issues Facing Semiconductor Companies Pressured to Get Products to Market

Verification engineers play an integral role in an electronic product’s success since they are responsible for integration verification, performing system verification and validation. They need the right tools and methodology to be successful. Semiconductor companies can arm their verification team with a new weapon to fight the SoC verification battle that will help them succeed in the consumer market and successfully battle low margins, fierce competition and aggressive pricing. Read More

May 31, 2012
Electronic Engineering Times: Lifting the System-Level Fog with SoC Verification

What’s left to do is to create a new subcategory called “SoC Verification” to highlight the special verification challenges posed by SoCs with embedded processors. Tools in this category, such as Breker’s TrekSoC, take a fundamentally different approach to verification by automating self-verifying embedded C test generation, intimately linking hardware and software together. Read More

May 3, 2012
Electronic Engineering Journal: Verifying Today’s SoCs Requires a New Approach

The size, complexity, and large number of shared resources in a contemporary SoC demand a new and innovative approach to verification. Leveraging scenario models to automatically generate self-verifying C test cases with connections to the testbench exercises both regular production operation and corner cases. Read More

April 13, 2012
EDA DesignLine: SoC Low-Power Verification Requires a Full-Chip Solution

The technique that has the highest impact on verification is perhaps the most widely used: power shut off (PSO). While simple in concept, PSO has many tricky aspects in implementation that must be carefully verified. Read More

February 1, 2012
Gabe on EDA: The Truth about SoC Verification

The truth about SoC verification: The SoC cannot be fully verified without running thorough automated self-verifying test cases on its embedded processors. Read More

November 1, 2008
Chip Design: Now Is the Time to Fix Coverage Metrics

By defining what exactly is meant by functional intent coverage, designers can make tests efficient. After all, each test exercises a specific combination of outcomes. At the same time, designers can retain the benefits of an automated approach, which allows computers to work on the verification problem instead of human beings. Read More

May 6, 2008
EDA DesignLine: Host Bus Adapter (HBA) Verification with Trek

The value of Trek is that it can generate deep state scenario from the Coverage Model and guarantee coverage closure. Read More

October/November, 2007
Chip Design: Three Views on Verification Challenges

Verification engineers now have the ability to cheaply synthesize high quality, targeted test cases that augment their existing verification flows. As a result, they can make efficient use of available simulation capacity to achieve coverage closure. Read More