Blog Posts « Breker Verification Systems

February 26 - March 1, 2018
Booth # 304
Double Tree Hotel, San Jose, CA

October 2, 2017
The Breker Trekker: Time To Be Heard

Accellera has just extended the review period for the Portable Stimulus Standard. The committee is now seeking comments up until the end of October. Breker would like to join the committee and say how important it is for users to get involved with this standard. While we, as vendors, have some experience in this area, we are not doing this day in and day out. We need your guidance and feedback. Read More

September 13, 2017
The Breker Trekker: Understanding Portable Stimulus Graphs

When people talk about the Portable Stimulus Standard (“PSS”) they throw around the term “graph based” as if that somehow clarifies everything. They usually don’t bother to describe what it means, beyond it being some simple mathematical model. Some vendors even confuse it with the term “graphical”. To simplify this confusion, for this blog we will use the term “visual”. This blog will answer questions about how PSS relates to graphs and how those graphs relate to other similar graph-based models already used within the industry. Read More

August 24, 2017
The Breker Trekker: Portable Stimulus Gains Momentum

Next month will see a significant milestone for Portable Stimulus. On September 15th the review period for the Early Adopter release of the Accellera Portable Stimulus Standard (PSS) will close and with it the opportunity to make your voice heard. This is an exciting time for Breker, the market leader in this space for the past decade, and signals a time when the industry can transition from a technology only available to a few aggressive adopters, to making it available to the mainstream. Read More

June 9, 2017
The Breker Trekker: Rewriting Revolutionary History

The semiconductor design industry has always preferred evolution over revolution. There have been a few successful revolutions but most of the time revolution happens over time through evolutionary steps. Read More

May 22, 2017
The Breker Trekker: Total Value of a Standard

The creation of the Portable Stimulus standard has raised a number of issues about the tradeoffs between using an industry standard language and a domain-specific language. Read More

April 4, 2017
The Breker Trekker: Portable Stimulus - The First Verification Model

When people think about design languages, they may not realize that the language is almost irrelevant. Read More

March 17, 2017
The Breker Trekker: Users Talk Back on Portable Stimulus

At the recent DVCon, I had the pleasure to moderate a panel that enabled users to talk about their experiences working with the Accellera standard’s body during the creation of the Portable Stimulus standard. Read More

February 23, 2017
The Breker Trekker: Portable Stimulus Takes Center Stage At DVCon 2017

When DVCon opens next week, attendees will hear plenty of talk about Portable Stimulus, a methodology and technology that’s grabbing industry attention and gaining momentum with the design verification community. In fact, I predict it will be the buzz of the conference this year. Read More

December 8, 2016
The Breker Trekker: Constrain Me, Please

In the movies, when a person acts irrationally they are usually declared to be mad and quickly placed in a straitjacket for the protection of themselves and those around them. If we continue those thoughts into the world of verification, SystemVerilog must be declared to be a mad language.   Read More

November 4, 2016
The Breker Trekker: EDA Hates C++. Wait, What - Back Up!

Why is Accellera supporting the use of an industry standard language in the development of the Portable Stimulus Standard? Read More

October 25, 2016
The Breker Trekker: The Genesis Of Portable Stimulus

When I first met Adnan Hamid, Breker’s CEO, his philosophical understanding of verification and its implications for electronics was as crystal clear then as it is now. He sees it as the enabler for greater innovation in chips and beyond, and takes it as his life’s mission. His passion was inspiring to me and I did not hesitate for a second when we decided to jointly start Breker. Throughout our journey, I have watched the market converge with what we are building at Breker, and have come to better appreciate my partner, the visionary man. Read More

September 29, 2016
The Breker Trekker: The Next Wave in Verification

The current work being done on Accellera's Portable Stimulus Working Group is your verification standard for the next twenty years. Read More

September 8, 2016
The Breker Trekker: User Victory in Portable Stimulus

Breker continues its advocacy for the user at the Portable Stimulus Working Group. Read More

September 1, 2016
The Breker Trekker: Hitting the Town with DVClub

We are pleased to let you know that we have signed up as a full sponsor for all 16 annual DVClub events in the U.S. and Canada. This year, these include four each in Silicon Valley, Austin, and greater Boston plus two in Portland and one each in Research Triangle Park (RTP) and Toronto.   Read More

August 24, 2016
The Breker Trekker: A Further Preview of DVCon India 2016

Congratulations to the DVCon India Technical Program Committee for pulling together such an interesting program. There should be topics of interest to just about anyone involved in design or verification. Read More

August 18, 2016
The Breker Trekker: Why Portable Stimulus Must Be Bidirectional

We always planned for, and enabled, bidirectional flow of our automatically generated test cases, but we have been surprised and pleased by how effective this ability has proven for our customers. Read More

August 10, 2016
The Breker Trekker: IEEE Reports that C is the Most Popular Programming Language

We have shown how all the layers required for a portable stimulus solution can be specified in standard C/C++ with no new constructs added to the language. It’s nice to see the latest IEEE survey re-asserting the popularity of C and its derivatives. Read More

August 3, 2016
The Breker Trekker: DVCon India Just Keeps Getting Better

The third annual DVCon India will be held on September 15 and 16, once again at the Leela Palace in Bangalore. From our perspective, the show just keeps getting better and better every year. Read More

July 27, 2016
The Breker Trekker: Guest Post: More on EDA Startups, Behemoths, Corner Stores, and Zombies

In order for the EDA industry to remain healthy and productive, both the customer side and behemoths must support the growth of innovation and help to turn startups and corner stores into mid-tier companies, which can thrive on their own and continue to drive the innovation that is mainly lagging from the majors. Read More

July 20, 2016
The Breker Trekker: Guest Post: Open Source Requires Open Minds, Especially in EDA Verification

Open Source could be the mechanism that allows the EDA vendors to sell their high value core engines into new markets, thus realizing the growth they need and are having trouble extracting from existing sources. Read More

July 14, 2016
The Breker Trekker: Evolution or Revolution in System-Level Verification?

Portable stimulus is “the next big thing in system-level verification” so the result is a revolution, but the effort involved is evolutionary. Read More

July 5, 2016
The Breker Trekker: The Return of EDA Startups, Behemoths, Corner Stores, and Zombies

The categories are the same, but there has been some movement. The behemoths have only grown bigger, with more than two dozen acquisitions small and large contributing. Read More

June 29, 2016
The Breker Trekker: Opening a TrekBox for Your Birthday

TrekBox is a highly flexible and valuable part of the overall Breker portable stimulus solution. It has far more tricks than a traditional simulation-only trickbox, but it retains the familiar concept of using memory-mapped locations for communication. Read More

June 22, 2016
The Breker Trekker: Automated, Realistic Performance Analysis for Your SoC

An appropriate TrekApp application can automatically generate test cases designed to stress specific aspects of your design with minimal user input. For example, our Cache Coherency TrekApp generates test cases carefully crafted to hit corner cases in multi-level caches. If you want to extend this verification to exercise IP blocks at the same time, you can add a TrekApp for a specific I/O protocol or extend the graph-based scenario model to provide information about your custom IP. Read More

June 15, 2016
The Breker Trekker: Electronics Trade Press, the Bell Tolls for Thee

As the cliché goes, the only thing constant is change. The electronics press outlets will continue to morph into new forms in response to both financial realities and reader preferences. Read More

June 9, 2016
The Breker Trekker: Report from Austin: BBQ, DAC, and Portable Stimulus

We had a lot of fun, gathered some very promising leads for new users, and observed that “portable stimulus” is clearly a big draw. That’s all good, because DAC returns to Austin for 2017. Read More

June 1, 2016
The Breker Trekker: Please Join Us at DAC to Catch Up on Breker’s Technology

Again this year, our CEO Adnan Hamid is participating in the DAC technical program. He will be presenting in the “How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges” session. Read More

May 19, 2016
The Breker Trekker: Path Constraints for Graphs and Portable Stimulus

At various times during the verification process, you may wish to focus on certain blocks in the design or combinations of blocks that provide specific functionality. Path constraints are an easy and natural way to control which paths are considered when a portable stimulus tool is generating test cases by traversing the graph. Read More

May 11, 2016
The Breker Trekker: SoCs in Space!

It would seem that many of the same arguments driving consumer products, server farms, and networking infrastructure to SoCs would apply to military-aerospace applications as well. Are there any fundamental barriers to making today’s most advanced chips available in space? Read More

May 5, 2016
The Breker Trekker: The Report of Simulation’s Death Was an Exaggeration

I assert not only that simulation is “not quite dead yet” but that it is very much alive. Breker preserves and even extends the value of simulation with efficient, automatically generated test cases, vertical reuse from IP to SoC, and seamless horizontal reuse to hardware. Read More

April 26, 2016
The Breker Trekker: Catching Up with Portable Stimulus

We felt that there was some confusion in the industry because of the “portable stimulus” term. First of all, any verification tests must include results checking and coverage in addition to stimulus. Further, the tests themselves do not need to be portable. Read More

April 19, 2016
The Breker Trekker: Designers and Verification Engineers: Living in Different Worlds Together

Here at Breker, we have seen our graph-based scenario models become popular with both designers and verification engineers, serving to communicate verification intent among different teams. I believe that portable stimulus will help bring architecture, design, verification, and validation all closer together. Read More

April 13, 2016
The Breker Trekker: EDAC Expands Its Scope but Misses an Opportunity

I can’t help wishing that EDAC had renamed itself the “Electronic System Development Alliance” as a first step toward acknowledging that the expanded scope of the organization and the EDA industry now includes even more people beyond hardware designers. Read More

April 5, 2016
The Breker Trekker: Merger Mania and the Still-Changing Semiconductor Landscape

There are quite few shifts in the Top 20 suppliers from 2015 to 2016, although some of them are only by a position or two. The most dramatic change occurred as the result of a deal mentioned above: NXP rose from number 15 to number 7 after its acquisition of Freescale, which disappeared from the rankings. Read More

March 30, 2016
The Breker Trekker: It’s Never too Early to Start Thinking about DAC

I encourage all of you to review the program and start making your own plans. You’ll be sure to have lots of fun in Austin, and on the basis of the information available today I’m sure that this will be a great show. Read More

March 24, 2016
The Breker Trekker: A Portable Stimulus Standard Will Take Time, but the Technology is Here Today

The portable stimulus standard will take some to complete for all the reasons we’ve discussed but the technology to implement it exists today. Please come join the ranks of Breker customers now, and we’ll migrate you to the standard when it’s available. Read More

March 16,2016
The Breker Trekker: A Snapshot Update on the Accellera Portable Stimulus Effort

We know that the majority of likely users of this standard are already C/C++ programmers. Leveraging C++ means no new language to learn and a minimal ecosystem for vendors to develop. Read More

March 9, 2016
The Breker Trekker: DVCon Panel: Trying to Define the ESL Shapeshifter

Portable stimulus can and will help to tie ESL into mainstream chip development. Some of our customers already use our tools to automatically generate tests for both high-level models and RTL (and beyond). Reuse of stimulus, results checking, and coverage from virtual prototypes to silicon, in either direction, is both part of the Accellera vision and a capability we deliver today. Read More

March 3, 2016
The Breker Trekker: Portable Stimulus Was Front and Center at this Year’s DVCon

The highlight of the show for us came on Tuesday morning, when Raja Pantangi from Cavium co-presented “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” with Breker CEO Adnan Hamid. Adnan discussed why cache coherency is such a challenging verification problem and Raja described a recent project in which Cavium needed to verify three SoCs containing a total of 144 CPU cores in the bring-up lab. Read More

February 24, 2016
The Breker Trekker: Automatically Generating Interacting, Self-Checking Test Cases for 144 CPU Cores

We generated test cases to verify all three SoCs together, containing a total of 144 CPU cores, 96 running cache coherency tests and 48 generating PCIe traffic. To be clear, the 144 programs we generated were not independent; all test cases were self-checking and multi-threaded, with the CPUs interacting and interleaving. Read More

February 19, 2016
The Breker Trekker: Why Is Cache Coherency So Hard to Verify?

It is almost impossible to imagine hand-writing interacting, self-checking cache coherency tests for a multiprocessor SoC running one on platform, let along making these tests portable. Breker’s approach to cache coherency is a very welcome alternative. Read More

February 10, 2016
The Breker Trekker: A Preview of the Upcoming DVCon in San Jose

Cavium develops some of the biggest chips in the world, including data center and cloud processors with 48 ARM cores. We’re proud to say that we played a role in the verification of these designs, especially cache coherency, and are grateful to Cavium for allowing us to discuss their project. Breker is back on the technical program Tuesday morning, as our founder CEO Adnan Hamid participates in the “Redefining ESL” panel. Read More

February 3, 2016
The Breker Trekker: Expanding Our Scope to Multi-SoC System Verification

TrekSoC-Si has automatically generated many test cases with more than 100 C files, all fully multi-threaded and coordinated, and the customer has run them in a multi-SoC configuration on real silicon in the bring-up lab. It’s a great demonstration of the power and extensibility of the Breker approach. Read More

January 27, 2016
The Breker Trekker: What Does Semi Merger Mania Mean for EDA?

Creative solutions from EDA vendors are needed now more than ever. Semi merger mania gives us all good reason for concern, but our industry is growing, and in the end the benefits of the ongoing changes may outweigh the downside. Read More

January 20, 2016
The Breker Trekker: Silicon Valley Still a Center of Semiconductor Innovation

If a lot of Silicon Valley companies are being acquired for their technology, then we are maintaining an edge in innovation. When local companies are doing the acquiring, this could be viewed as positive for semiconductor leadership here, or perhaps a bit negative since we’re looking elsewhere to find innovation. Read More

January 12, 2016
The Breker Trekker: When Did CES Become the Chip Education Show?

Chip manufacturers will link their products with consumer devices to give systems vendors ideas for applications and to try to build brand identification and loyalty among end users. Read More

January 6, 2016
The Breker Trekker: Revisiting System / Scenario / Use-Case Coverage

The best way to specify system coverage is with a graph-based scenario model. The graph shows all the possible use cases for the chip, including how multiple IP blocks in a single SoC can be strung together for application-level scenarios. These represent how the chip is actually used by the end consumer. Read More

December 30, 2015
The Breker Trekker: Top 5 Latest Holiday Gifts for the Verification Engineer

There has been much discussion in the industry about how EDA must expand into new territory given the ongoing consolidation of its semiconductor customers, with embedded systems often mentioned as fertile ground. Breker is already there given how our customers use our tools today. Read More

December 22, 2015
The Breker Trekker: Frontiers of Microprocessor Test and Verification

The Altera talk on “Verification of a Cache Coherent system with an A53 cluster using ACE VIP with Graph Based Stimulus” was given by Perry Wobil. The use of the term “graph” suggests that Breker might have been involved, and in fact this project used our TrekSoC and Cache Coherency TrekApp products as a key part of the verification process. Read More

December 16, 2015
The Breker Trekker: Report from the 16th MTV Workshop

I pointed out that there was no “wishful thinking” about portable stimulus at all. Breker’s customers have been automatically generating portable stimulus, results checking, and coverage for years. Read More

December 10, 2015
The Breker Trekker: Mystic Secrets of the Graph – Part Three

We transform system-level coverage into SystemVerilog cover groups and output the results. You can then import our system-level coverage into your existing coverage viewer (simulator, verification planner, Verdi, etc.) to combine it with the traditional coverage metrics. This closes the loop; you start with a graph-based scenario model that represents your verification intent and we report the results against your coverage-based verification plan. Read More

December 3, 2015
The Breker Trekker: Mystic Secrets of the Graph – Part Two

If this graph was being used to test a car whose reverse gear was broken, the graph could be constrained so that the reverse option would never be selected for the gear. This situation is quite common in SoC verification when some of the RTL has not yet been implemented and so it makes no sense to generate test cases yet for that part of the design. Read More

November 24, 2015
The Breker Trekker: Mystic Secrets of the Graph – Part One

Graph-based scenario models are really quite simple in concept: they begin with the end in mind and show all possible paths to create each possibly outcome for the design. Thus, they look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. Read More

November 17, 2015
The Breker Trekker: Why C/C++ Is the Lingua Franca for Verification

We have shown in a series of posts how a portable stimulus solution can be supported by C/C++ and a simple application programming interface (API). We believe that this is the best approach for the standard because so many of the engineers who will write portable stimulus models already know C/C++ and are comfortable with that input format. Read More

November 11, 2015
The Breker Trekker: Verification Languages: Tower of Babel?

We’ve argued before, in the context of a portable stimulus standard, that C/C++ is the closest thing we have to a universal verification language. We presented a series of posts in which we showed how all three layers required by a portable stimulus solution can be supported by C/C++ and a simple application programming interface (API). No new constructs or new languages are needed. Read More

November 3, 2015
The Breker Trekker: Invention Protection: Patently Obvious or Patently Absurd?

The ability to obtain a patent is a motivation to invest in IP and inventions. For other companies in similar fields, the existence of the patent drives them to innovate in different directions, possibly coming up with entirely new solutions to the same problems. Alternatively, they could develop extensions that build on the patent, opening the possibility of cross-licensing with the original patent holder. Read More

October 28, 2015
The Breker Trekker: The Secret Decoder Ring for Formal Analysis

He described a combination of a hardware-supported hypervisor and a trusted execution environment support by ARM’s TrustZone technology. There are opportunities for formal to verify parts of this solution, but my main reaction is that graph-based scenario models would be a great fit to this system-level hardware/software approach. Read More

October 22, 2015
The Breker Trekker: Report from the 2015 Silicon Valley IP Users Conference

The most provocative question that Ed asked the panelists was whether the IP industry is mature, or still an “awkward teenager.” The consensus tended toward the latter, with comments that this is in many ways a good thing. Lack of maturity also means lack of calcification. IP companies can still be flexible in their business models, there is plenty of room for innovation by small IP suppliers, and the IP industry is growing faster than traditional EDA. Read More

October 16, 2015
The Breker Trekker: Sage Advice for Startups

When Breker relocated our headquarters from Austin to Silicon Valley four years ago, the main reason was to have better access to experienced entrepreneurs who could help guide the company to success. Michel is just the sort of person our founders had in mind, and he has been generous with his time and talent. Read More

October 7, 2015
The Breker Trekker: Merger Mania in the Semiconductor Industry

M&A activities are a mixed blessing. Many engineers in the acquired companies worry about loss of local control of technology and loss of jobs. However, acquirers usually value targeted public companies considerably higher than the stock market, so many employees may share the benefit of a good deal. For private companies, acquisition offers an alternative exit strategy to the increasingly rare IPO. Some will win and some will lose, but the trend is highly likely to continue. Read More

October 2, 2015
The Breker Trekker: The Results Are In, and Graphs Win!

All three EDA vendors with current products claiming to deliver some level of portable stimulus have agreed upon a graph-based input specification format. We’ve pledged not to reveal details of what’s going on within the PSWG, but we believe that it’s fair to say that all contributions under consideration are based on graphs. And so, on this basis, we claim that graphs have “won” by being selected as the enabler for portable stimulus. Read More

September 23, 2015
The Breker Trekker: There Is No Silver Bullet for Low-Power Verification

There is no silver bullet for verification. The problem is both so broad and so deep that no single tool or technology will ever satisfy the need. It takes a mix of solutions, guided by methodologies, to have any chance of first-silicon success. Low-power verification is an area where this is especially true, and unfortunately there is no silver bullet to be found here either. Read More

September 16, 2015
The Breker Trekker: Riding the Portable Stimulus Wave

We shook up the industry a bit last week, but with the goal of crafting a first-rate portable stimulus standard as quickly and efficiently as possible. The high level of interest throughout DVCon India was more evidence that the time has come for graph-based and software-driven verification to become mainstream technology. Read More

September 8, 2015
The Breker Trekker: Breker, Cadence, and Mentor Accelerate Portable Stimulus Standard

We can’t predict the future, but we fully expect that the development of the standard will be accelerated significantly by this move. In turn, we anticipate wider and faster adoption of portable stimulus in the industry. Accellera encourages exactly this kind of multi-company cooperation in order to produce quality standards in a reasonable timeframe. Read More

September 2, 2015
The Breker Trekker: Life on the Embedded-EDA Frontier

We work on most customer projects with one foot in the traditional EDA verification space and the other in the embedded domain. We’re comfortable in both places, working with any mix of engineers. Read More

August 25, 2015
The Breker Trekker: Are Verification and Validation Different? Does Anyone Care?

Breker is mostly about SoC verification, just as our company descriptor claims. Since our whole verification approach is built on realistic use cases that stress the limits of the hardware design more than production code ever would, we are arguably validating the hardware design as well as verifying it. Read More

August 20, 2015
The Breker Trekker: The Second DVCon India Looks Even Better than the First

Portable stimulus will be front and center in the program. The very first technical session slot features long-time Breker users from IBM on “Walking the Graph” and we’re looking forward to that paper. Read More

August 12, 2015
The Breker Trekker: Industry Drivers for DVCon India

The second DVCon India is less than a month away, on September 10-11 at Leela Palace in Bangalore. I have every expectation that portable stimulus will be a major theme again. Read More

August 5, 2015
The Breker Trekker: Life on the Hardware-Software Frontier

We automatically generate software test cases to verify hardware, so we’re naturally somewhere along the frontier. Beyond that, our users often include existing HdS such as bare-metal drivers in their scenario model descriptions to reduce the size of their graph. To the extend that portions of this code is reused in the production drivers, we are effectively helping to verify some of our customer’s SoC software as well as their hardware (RTL code). Read More

July 30, 2015
The Breker Trekker: Using Scenario Models to Capture Use Cases

Each user-level scenario is the same as “use case” and, in fact, we’ve often used the term “realistic use cases” ourselves. Among the tasks to be tackled by Accellera’s Portable Stimulus Working Group (PWSG) as SoC verification matures is settling the industry terminology. Read More

July 23, 2015
The Breker Trekker: Congratulations to Richard Goering for a Great Career

Richard had a great career that brought much value to our industry. Some of his colleagues continue to cover EDA well, but it won’t be quite the same without him. Given all the changes that have occurred for magazines and newspapers, plus the multiplicity of online sources, we will probably never again see so much influence from a single individual. Read More

July 15, 2015
The Breker Trekker: Guest Post: Rain or Shine for the EDA Cloud?

We have discovered, as with many EDA developments, that the pull of a significant capability, such as verification performance, will drive the cloud where a business model change will not. The security concern is set to dissipate over time, especially when traded-off for time to market at the management level. Read More

July 7, 2015
The Breker Trekker: Some Fond Memories of EDA Analyst Gary Smith

Gary did outstanding work building the EDA team within Dataquest and achieving the impressive title of Managing Vice President. In 2006, when Dataquest decided that they would no longer track the industry, Gary didn’t miss a beat as he established Gary Smith EDA as an independent consulting and analysis company. Read More

June 30, 2015
The Breker Trekker: What’s so Special about Your SoC Design Data?

People say that they’re nervous about EDA in the cloud at the same time that the engineers on the project and the companies themselves have virtually every other precious corporate data asset in the cloud already. Read More

June 24, 2015
The Breker Trekker: Is the Forecast Cloudy Yet for EDA?

The final user concern is security of their system-on-chip (SoC) design and verification data in the cloud. We noted two years ago that this was the biggest barrier to adoption, and it may well still be the case today. IBM notes that it is already a major cloud player, so EDA users may be more willing to trust data there than on “that bookseller’s cloud” or in a cloud provided by an EDA vendor. Read More

June 17, 2015
The Breker Trekker: Please Help Us Choose Our Next TrekApp

There are many other trends ongoing and emerging in the SoC industry, and we have a long list of ideas for possible TrekApps to help address the challenges that are arising. We would like your help in prioritizing our development efforts. Read More

June 11, 2015
The Breker Trekker: A Look Back at the 52nd DAC

It was a really good show for us. Our transformation of last year’s “Ice Breker” booth to be more open and inviting seemed to work; we had many visitors and quite a few compliments. We were happy with our representation in the program and with all the interest in portable stimulus solutions. Next year DAC returns to Austin, and of course we will be there and look forward to seeing you. Read More

June 2, 2015
The Breker Trekker: Please Join Breker at DAC in San Francisco

We’re also highlighting the fact that we have a robust, proven solution for portable stimulus available now. Our Trek family of products meets every Accellera requirement and has been used to verify some of the biggest, toughest chips in the world. 100 ARM cores running in parallel in real silicon? Graph-based scenario models with more than a million nodes? Massive GPUs? We’ve verified all these and more. Read More

May 28, 2015
The Breker Trekker: Portable Stimulus Layer 3: Test Randomization

We want to stress that this is a native language solution to both graph specification and portable stimulus generation. There is no new language to learn, no new constructs, no extensions to existing languages, or anything of the sort. The API can easily be offered in multiple languages; C/C++ and SystemVerilog are two obvious choices. Verification engineers use API-enabled libraries all the time, so adding one for portable stimulus is a very natural approach. Read More

May 20, 2015
The Breker Trekker: Portable Stimulus Layer 2: Test Scheduling

The idea of a base-class library accessed by an API is very familiar to verification teams. They already use library calls to set up their testbenches, configure their registers and memory, run their tests, and check their results. Adding in the first layer of portable stimulus makes their tests both vertically reusable from IP to SoC and horizontally reusable across different platforms. The second layer enables control of scheduling and resource sharing. Read More

May 14, 2015
The Breker Trekker: Portable Stimulus Layer 1: Test Abstraction

There are several advantages of our proposed approach to the Accellera portable stimulus standard. The layering clearly defines what’s needed for each automated verification task. The library approach is familiar to users of the UVM and other Accellera standards. There’s no new language to learn, so engineers can get up and running quickly. Read More

May 7, 2015
The Breker Trekker: Options for a Portable Stimulus Specification Format

As you would expect, we strongly believe that a graph is the best abstraction for specifying a design’s control flow. A graph-based scenario model shows how IP blocks are interconnected to form use-case scenarios and all the options available. The notion that each test can be generated by walking the graph and making randomized choices for each decision (“select node”) is easy to understand. Read More

April 29, 2015
The Breker Trekker: What Does “Portable Stimulus” Really Mean?

We do not believe that the tests themselves can be made portable. The same bits that run on simulation, leveraging UVM testbench models and backdoor memory access, cannot possibly run on actual silicon. What can be portable, and standardized, is some sort of abstract specification or model for the verification space and the test desired. Read More

April 23, 2015
The Breker Trekker: DAC, DVClub, DVClub Europe, DVCon, DVCon Europe, DVCon India: Verification is Everywhere

Perhaps the biggest cliche in EDA is that functional verification consumes 70% of a chip project’s resources and is growing. Variations on this statistic have been around for at least ten years, probably more. It’s quoted almost as much as Moore’s Law, which incidentally turned 50 this year. Although not as old, the observation that verification dominates SoC development is almost universally accepted. Read More

April 16, 2015
The Breker Trekker: The Ever-Changing EDA Landscape

We can still make some observations about the EDA industry based on our knowledge and the information available from the public companies. The most obvious trend is one of consolidation. All three major vendors have grown via acquisitions as well as organically. In fact, most of the middle tier of EDA has disappeared as the companies have been acquired by the top three. Read More

April 8, 2015
The Breker Trekker: The Ever-Changing Semiconductor Landscape

Broadcom first made the top 20 list in 2005, and in less than ten years climbed to number eight. Hynix has grown steadily since its debut in 2001, and as of 2013 is in fifth. Micron has risen to number four with a big leap due to the acquisition of Elpida. Perhaps Qualcomm has had the most dramatic rise, entering the top 20 in 2003 and now achieving the coveted third spot for two years in a row. Read More

April 2, 2015
The Breker Trekker: A First Look at the Program for the 52nd DAC

I’d like to bring your attention specifically to the IBM talk “Walking the Graph: A Holistic Approach to Graph-Based Verification for Logic with Sparse State Space” in the second session listed above. This group is a long-time Breker customer and a strong industry advocate for using our graph-based scenario models.   Read More

March 26, 2015
The Breker Trekker: Our Case Study of Verdi Integration from SNUG

The goal of the project was to integrate the Breker product line, specifically the TrekBox run-time module, with Verdi and Verdi HW SW from Synopsys. Verdi is an industry-leading debug platform for RTL design and verification; Verdi HW SW is an extension that supports software running on embedded processors within the design. We were interested in this integration to provide our mutual customers a better debug experience when one of our automatically generated test cases triggers a bug in a customer design. Read More

March 18, 2015
The Breker Trekker: Please Join Us at SNUG Silicon Valley Next Week

We found a considerable contingent of verification engineers at SNUG, many of them receptive to our message that new solutions are needed in the SoC era. This has not been the case at some of the other single-vendor events we have attended, so our thanks to Synopsys and the SNUG team for drawing verification users. Read More

March 10, 2015
The Breker Trekker: Decoding Formal Club Unlocks Some Mysteries

In formal analysis, as in graph-based SoC verification, constraints are essential. They ensure that only legal state space is explored and offer the verification team ways to fine-tune what is being verified and where the focus should be.   Read More

March 5, 2015
The Breker Trekker: It Was a Great DVCon, and There Are Two More to Come

As we noted recently, the world is moving in Breker’s direction. For the first time ever at a trade show, the majority of the people who stopped by our booth had previously heard about us, and in many cases specifically had us on their list of vendors to visit. We’ve been talking about SoC verification, graph-based scenario models, realistic use cases, and automatically generated self-checking test cases for several years. It is clear that more and more people are listening. Read More

February 24, 2015
The Breker Trekker: The Importance of DVCon and Why Breker Will Be There

Our theme this year is simple: “Portable Stimulus and Tests Available Now!” Two weeks ago we talked about the new Accellera Portable Stimulus Working Group and its charter to “develop the electronic industry’s first standard for portable test and stimulus.” We are actively participating in this group already and are committed to a leadership role in creating the new standard. But in the meantime, we want to be clear that we have a proven solution today providing both vertical reuse from IP to SoC and horizontal treuse across all verification platforms. Read More

February 18, 2015
The Breker Trekker: Six Points of Connectivity with the Synopsys Verification Flow

The import of Breker’s coverage metrics also means that coverage targets identified in Verification Planner can be satisfied by the TrekSoC test cases, with credit given in the original verification plan. This is the sixth point of our integration with the Synopsys verification flow but it surely will not be our last. Additional projects underway or planned will be discussed in this blog when results are available. Read More

February 11, 2015
The Breker Trekker: Please Welcome the Accellera Portable Stimulus Working Group

We would like to see the scope of the standard, and ideally even the group’s name, widen to include results checking and coverage as well as stimulus. Perhaps “portable test cases” would be a more accurate term. Also, while the PSWG was not formed specifically to standardize graphs, we still believe that graphs are the best known way to accomplish both portability and other important verification benefits, but are open to other methods that the working group may consider.   Read More

February 5, 2015
The Breker Trekker: What to Run on Day One in SoC Simulation

The test cases generated by TrekSoC provide an excellent solution. They run on bare metal, so do not require booting an operating system, kernel, or monitor of any kind. They are carefully crafted to run efficiently in simulation, offloading as much as possible from the SoC model. Read More

January 27, 2015
The Breker Trekker: The Evolution of DesignCon and Why Breker Isn’t There

I mentioned that Breker exhibited at the annual Design and Verification Conference (DVCon) in San Jose, and we’ve since published several popular posts about that show. It remains the most important event for us, our customers, and the functional verification industry in general. We will be there again in March, and will provide more information in an upcoming post. I also mentioned the DesignCon show, held annually in Santa Clara, but did not list it among those that we attend. Read More

January 20, 2015
The Breker Trekker: What to Run on Day One in the Bring-Up Lab

The sheer number of test cases than you can run in your lab provides even more stress on the design and exercises even more of the SoC’s capabilities. We also detect basic issues with your download and lab set-up, easier and faster than hand-written tests since our test cases are self-checking with better debug capabilities. We even provide coverage metrics from test cases running in silicon, a unique feature. For all these reasons, we recommend that our test cases be run on Day One when your chip arrives from the foundry. Read More

January 14, 2015
The Breker Trekker: What to Run on Day One of Emulation

It’s inefficient to write new tests and hard to adapt existing tests for each new platform. From the same graph-based scenario model, our products generate test cases tuned for each platform, from simulation and acceleration through ICE, prototypes, and silicon. We recommend that our test cases be run on Day One. Read More

January 7, 2015
The Breker Trekker: Blast from the Past: Verification in Silicon

What we’re starting to see is the truly stunning trend that some teams are taping out SoCs without ever having run the entire design together. This means that full-chip verification and debug isn’t happening until first silicon is in the lab. Read More

December 30, 2014
The Breker Trekker: Top 5 New Holiday Gifts for the Verification Engineer

When you run a test case generated by one of our Trek family of products, it may fail. This may be due to an error in the chip design itself, an error in your testbench, or an error in your scenario model. When such an error occurs, you want to debug it using the same technology you would use for one of your own hand-written tests. Read More

December 23, 2014
The Breker Trekker: Just What is a “Breker” Anyway?

A play on “breaker” for the name seemed obvious, but Adnan didn’t want confusion that he might be demolishing buildings or verifying circuit breakers. In the end, “Breaker” became “Breker” and the rest is history, or rather history in the making since we’re still a young company. Read More

December 16, 2014
The Breker Trekker: Guest Post: What's in a Name?

Naming companies and products is big business. In fact, an entire industry is devoted to coming up with the perfect name to neatly express a company’s mission and the product portfolio. In some cases, though, companies stick closer to their employees and have contests where they can suggest names. Read More

December 11, 2014
The Breker Trekker: A Math Question: Does IoT = SoC?

As long as more nodes are added to the Internet and more SoC devices are designed, the need for verification and the opportunity for innovative solutions will continue to grow. That will be good news for us and we will continue to evolve our product line as needed for our IoT customers. Read More

December 2, 2014
The Breker Trekker: Verification Needed to Take High-Level Synthesis Mainstream

We generate test cases that do an excellent job of stressing your design. Further, these test cases are fully portable from high-level simulation environments such as virtual platforms to traditional RTL simulation. No rework at all is needed to re-run the test cases. We can’t offer a formal guarantee but at least we can stress-test both versions of your design. Read More

November 25, 2014
The Breker Trekker: If Your Chip Is Not a Cache-Coherent SoC, It Soon Will Be

Simple bus-based SoCs, non-SoCs such as networking chips, and arrays of processors are all moving toward multi-processor, shared-memory, multi-level-cache-coherent SoCs. It is precisely this industry transition that is driving intense interest in TrekSoC, TrekSoC-Si, and our Coherency TrekApp. As this transition happens, cache coherency moves from the domain of the CPU architect to become a problem for everyone designing and verifying SoCs. Read More

November 18, 2014
The Breker Trekker: Will Breker Become an IP Company?

Although Breker is an EDA company and not known for IP products, we intersect with semiconductor IP (SIP) and verification IP (VIP) in important ways as we work with our customers. We’re also starting to offer our own scenario model IP (SMIP) as part of accelerating and improving verification even more. Read More

November 13, 2014
The Breker Trekker: Some Thoughts on SIPs, VIPs, and SMIPs

We do not generally advertise ourselves as being in the IP business. This is changing, as we hinted when introducing our Coherency TrekApp and the scenario model IP (SMIP) that underlines it. Read More

November 5, 2014
The Breker Trekker: If Your Chip Is Not an SoC, It Soon Will Be

Chips are moving to SoCs and SoCs are demanding multi-processor cache coherency. TrekSoC and our Coherency TrekApp are out-of-the-box solutions for verifying pre-silicon multi-processor cache coherency and measuring performance under realistic system stress. TrekSoC-Si extends these benefits to hardware platforms (emulators, FPGA prototypes, and silicon in the lab) all the way to post-silicon validation. Read More

October 30, 2014
The Breker Trekker: If Your SoC Is Not Cache Coherent, It Soon Will Be

What if you don’t have multiple processors or caches in your SoC design? There’s a clear sense emerging in the industry that more and more chips are becoming multi-processor SoCs, and most of these will require cache coherency for the CPU clusters and beyond. Read More

October 22, 2014
The Breker Trekker: Performance Verification: Bringing Your SoC to Its Knees

With Breker, you can enter into a much easier and more effective era of SoC performance verification. You can start with the our app to verify cache coherency while watching your processor and memory subsystem performance. You can extend the coherency graph to cover other coherent agents and IP blocks in your design, and completely your system-level verification of both functionality and performance. Read More

October 16, 2014
The Breker Trekker: Report from the Silicon Valley IP Users Conference

The IoT offers a great opportunity for Breker. Many of you will be spinning application-centric SoCs with few design changes for each variation, on very tight schedules that will permit no chip turns. This will put more pressure than ever on verification. Our ability to reuse scenario models from block to chip, across verification platforms, and between projects will be essential to meet IoT schedule and quality goals. Read More

October 8, 2014
The Breker Trekker: DVCon India: Harbinger of a Great SoC Future

There are many reasons that India has made so much progress so quickly in electronics: excellent education, English as a common language, democratic values, etc. These remain in place and so I fully expect that growth will continue and we will see more and more amazing SoC designs being developed in India. Read More

October 3, 2014
The Breker Trekker: Was DVCon India Really the Portable Stimulus Conference?

Thursday at DVCon India truly was Portable Stimulus Day. This reflects the importance of providing a better solution for verification reuse in the industry as well as the broad interest in Accellera’s efforts to work toward a standard. But it also reflects the emergence of India as a developer of chips as complex as any in the world and the intense need there for more automated and more thorough verification. Read More

September 23, 2014
The Breker Trekker: Breker and Carbon Team Up to Provide Fast, Accurate SoC Verification

Our first offering builds on Carbon’s Cortex A15 CPAK, which features the four-core ARM Cortex-A15 processor. The scenario model that ships with our version of the CPAK generates complex four-processor test cases “out of the box.” This level of activity stresses the model enough that you can make performance measurements and identify possible bottlenecks. Read More

September 17, 2014
The Breker Trekker: A Concise History of the Breker Product Line

We have a bunch of smart people with lots of ideas about how graphs can be applied to a wide range of problems. However, by focusing on the functional verification of large, complex chips using graph-based scenario models we are able to target a fairly specific group of companies and users. We also get tremendous productivity from a small R&D team because their collective knowledge spans the limited but important product range that we cover. Read More

September 9, 2014
The Breker Trekker: See Breker at Four Shows in Four Locations over Four Weeks

What verification engineer doesn’t love the occasional conference? It’s a chance to get out of the cubicle farm, hang out with colleagues from other companies, listen to stimulating technical talks, and catch up on what EDA, IP, and semiconductor vendors have been doing. Even in a time of tight travel budgets, the right conference can provide dividends far beyond its cost. There are a lot of smart people in the electronics industry and it’s valuable to share problems and solutions with them. Read More

September 2, 2014
The Breker Trekker: Cache Coherency? Breker Provides An App for That

The Breker Coherency App provides a graph-based scenario model pre-populated with most information needed to verify cache coherency. Of course, you need to provide the details of your system, including number of CPUs, number of threads, memory organization, and cache structure. We provide documentation, training, and applications support to walk you through the essential steps. Read More

August 29, 2014
The Breker Trekker: Preview of an Exciting New Show: DVCon India

If you’re doing design or verification in India, or you can possibly travel there, I highly recommend attending DVCon India. It’s certain to be educational and fun as well. Please be sure to attend our two tutorials if you can. Thanks, and we’ll see you in Bangalore. Read More

August 20, 2014
The Breker Trekker: Composition, Chaining, and Vertical Reuse with TrekUVM

TrekUVM fosters vertical reuse for chips with transactional UVM testbenches in much the same way that TrekSoC supports reuse for system-on-chip (SoC) designs with embedded processors. There is no known technology that supports reuse and test case portability better than our graph-based scenario models.   Read More

August 14, 2014
The Breker Trekker: Introducing TrekUVM: Enhancing Transactional UVM Testbenches

That’s where TrekUVM comes in. We’ve stripped out all the SoC-related technology and introduced a product that uses our familiar graph-based scenario models to generate transactional test cases well beyond what a UVM testbench can do with constrained-random stimulus alone. TrekUVM connects simply to all existing UVM verification components (UVCs) and can be adapted with little effort to support other testbench methodologies (OVM, VMM, custom, etc.) Read More

August 7, 2014
The Breker Trekker: Transactional Design Verification with TrekSoC

So we’ve followed a different path than our last blog post but ended up at the same point: in addition to SoCs, Breker knows how to verify large, complex chips that do not contain embedded processors. We’ll continue filling in the details in our next blog post, focusing on chips such as routers, switches, bridges, and modems.   Read More

July 30, 2014
The Breker Trekker: Verification Reuse from Transactional Testbenches to Embedded C Code

While some types of modems, switches, and routers have processors, many do not. Can TrekSoC verify these non-SoC designs? The answer is a resounding “yes!” After all, TrekSoC already has to understand how to talk to non-processor peripheral interface UVCs in the UVM testbench. If the design has only those interfaces, there is no requirement that a processor or processor bus must be involved. Read More

July 22, 2014
The Breker Trekker: A Guide to Composition for Graph-Based Scenario Models

The verification team invests a relatively small amount of effort into specifying the graph, and in return all test cases and a major portion of the testbench are generated entirely automatically. The return-on-investment (ROI) for scenario models is even higher when vertical reuse is taken into account. Unlike virtual sequencers and scoreboards, graphs are composable when moving from lower to higher levels of the design. Read More

July 17, 2014
The Breker Trekker: A Guide to Composition for Testbench Elements

The shortcomings of the UVM for vertical reuse is one of the factors that led Accellera to form the Portable Stimulus Proposed Working Group. As we’ve discussed, we are very active in this effort and believe that graph-based scenario models are an excellent way to take the next steps beyond the UVM. In our next blog post, we’ll show specifically how graphs enable vertical reuse and how they allow block-level verification elements to be composed at  the cluster and full chip levels.   Read More

July 8, 2014
The Breker Trekker: Would You Rather Push on a Rope or Pull It?

In the last six months or so, we have started hearing from more and more non-SoC teams that they are having difficulty full verifying their large chips with the UVM alone. They are finding it hard to stimulate targeted deep behavior purely by applying constrained-random stimulus on the inputs. We use the term “pushing on a rope” for this dilemma because it’s hard to steer stimulus from the inputs alone.   Read More

June 30, 2014
The Breker Trekker: Beginning with the End in Mind: Graphs and Formal

Graphs are still somewhat of a specialty technology, but part of Wolfgang’s argument is that they’re easy to understand since people are already used to formal tracing backward from goal to inputs. I found this to be a valid point, and another indication that graph-based verification is no longer regarded as an exotic technology. In fact, I think that graphs are easier to build and use than many of the complex assertions design and verification engineers write for formal analysis.   Read More

June 23, 2014
The Breker Trekker: Final DAC Roundup: Spotting Trends and Catching Frisbees

DAC feels as if it is in transition. Fifteen years ago, it was all about EDA. There were tremendous issues in design and all kinds of new companies springing up with innovative tools. Now, there are some new companies, but the design flows have become standardized and the rampant innovation has moved into other areas. DAC appears to be moving to more of a systems show; witness the growing recognition of IP and this year’s automotive pavilion. Read More

June 16, 2014
The Breker Trekker: Guest Post: DAC From a Different Perspective

This is the first DAC where I wasn’t responsible for an exhibitor booth and it was exhilarating. I was able to attend sessions, walk the exhibit floor and, generally, get a feel for what’s going on in our industry. I’m pleased to report the news is good. Very good, in fact. Read More

June 10, 2014
The Breker Trekker: Guest Post: How I Spent My Three Days at DAC

On the other end of the spectrum from Solido and CLK is Breker Verification Systems, a DAC exhibitor breaking new ground at the system level and the owner of this blog. I managed to wander by its booth and saw that its SoC verification solution garnered quite a bit of attention from DAC attendees. It, too, will enable better verified chips in those IoT devices.   Read More

June 5, 2014
The Breker Trekker: A Fond Farewell to DAC 51 in San Francisco

There is no doubt that  big forces in the industry are aligning toward our view of SoC verification with graph-based scenario models. Many of the people who stopped by our “USS Ice Breker” booth completely understood that they risked hitting an iceberg with their minimal full-chip verification efforts.   Read More

May 28, 2014
The Breker Trekker: DAC is Back! A Preview of the San Francisco Show

We’re most excited about our brand-new second demo, which shows our TrekSoC GUI integrated with the Synopsys Verdi Advanced Debug environment. You can launch our TrekBox GUI application from within Verdi and then freely navigate while all windows in TrekBox and Verdi remain synchronized for maximum debug efficiency. Read More

May 20, 2014
The Breker Trekker: Guest Post: DAC, the Industry Marathon to Beat All Industry Marathons

DAC is one of the few times each year when their company is able to present who and what it is in an environment different than the website, a one-on-one sales call or any other marketing program.   Read More

May 13, 2014
The Breker Trekker: To Standardize or Not to Standardize, That Is the Question

Let’s make the Breker position clear. We will participate actively in the PWG. If the industry decides to form a Working Group, we will join Accellera and will continue to participate actively. Finally, if Accellera issues a call for donations or contributions, we will submit our specification format for consideration. Read More

May 6, 2014
The Breker Trekker: Building a Productive Team for New Verification Approaches

There is very little expertise in the industry on using graphs for verification, and so we had to design our products to be usable by everyday verification engineers. Learning how to specify the graph is really quite easy and no special knowledge is required. I was delighted to see this; my biggest concern on joining Breker was that graphs would be a significant barrier to adoption.   Read More

April 29, 2014
The Breker Trekker: Extending Verification Planning to Formal and Graphs

TrekSoC uses a graph-based scenario model as its input, and as we’ve discussed before, graphs automatically provide a high-level form of system coverage. This coverage corresponds to specific features in the verification plan but also to combinations of features into realistic user scenarios. Since the Unified Coverage Interoperability Standard (UCIS) supports the importation of external coverage types, compliant verification planning tools can read in system coverage and merge it with other forms of coverage for a comprehensive view. Read More

April 22, 2014
The Breker Trekker: April 21, 2014: A-Day for Formal Analysis

I’m truly excited to be a pioneer again in the SoC verification market. I believe that we can revolutionize full-system verification as completely as formal analysis transformed block-level verification and formal applications automated many types of chip-level checks. I look to the success of Jasper as a good model for Breker and other EDA companies pioneering new approaches.   Read More

April 15, 2014
The Breker Trekker: Ruminating about Accelerating, Emulating, and Prototyping

I want to dig a bit deeper on hardware platforms in general. Historically, such platforms have been divided into three categories: simulation acceleration, in-circuit emulation (ICE), and FPGA prototyping. The reality is that these are no longer clearly distinct categories; there is a lot of fuzziness and even some overlap.   Read More

April 8, 2014
The Breker Trekker: The Dawn of the Embedded Verification Engineer

When customers adopt TrekSoC to automatically generate C tests cases rather than hand-write tests, some of the users are verification engineers and some are embedded programmers, so the embedded verification engineer is the perfect fit. Read More

April 1, 2014
The Breker Trekker: Coverage from Running SoC Silicon? How Is That Possible?

The secret here is that we can predict system-level coverage with 100% certainly when we generate the test cases. Scenario models are graphs, so we can explore them completely and understand every path that we have and have not walked through the graph in the process of generating test cases. We display the coverage results before you even run, whether in simulation, silicon, or any platform in between. You will achieve that exact coverage once you’ve actually run the test cases.   Read More

March 25, 2014
The Breker Trekker: Visibility into Running SoC Silicon? Tell Us More!

We especially want to stress that we provide exactly the same level of visualization for a multi-threaded, multi-processor test case running deep inside an actual chip as we do when it’s running in simulation or simulation acceleration.   Read More

March 19, 2014
The Breker Trekker: Please Visit Us at SNUG Silicon Valley Next Monday

Next week is the 2014 edition of SNUG Silicon Valley, and we want you to know that Breker will be there. Specifically, we will have a booth in the Designer Community Expo on Monday, March 24 from 4:00 pm until 8:00 pm. The Expo will be held, along with the technical sessions, in the Santa Clara Convention Center. This facility was recently expanded and upgraded, making it one of the best convention venues in the area. Read More

March 10, 2014
The Breker Trekker: Final Report on the Big DVCon 2014 Show

Anyone in EDA can tell you that the applications engineers burn some midnight oil refining the demos, and it’s not unusual for R&D to be scrambling to fit in a few final features that will give the demos more impact. Everything came together nicely and we had a very good turnout at the booth. Read More

March 4, 2014
The Breker Trekker: Half-Time Report from DVCon in San Jose

We saw a diverse group of engineers stopping by our booth. They spanned the full range of the SoC development process, ranging from high-end system architects all the way to silicon  engineers worried about production test vendors. Breker’s family of products is the only industry solution covering this entire range, so we believe that many of our visitors will engage in deeper discussions with us. Read More

February 25, 2014
The Breker Trekker: Sound the Trumpets! It’s DVCon Time Again!

Our focus in the booth is the many new features added to our flagship TrekSoC product since last year’s show as well as the TrekSoC-Si product we introduced late in 2013. You can see a live demo with TrekSoC-Si generating a test case, downloading it into a commercial SoC (a TI OMAP4430), and running in the actual chip. This shows our ability to support all verification platforms, from ESL and RTL simulation through acceleration, emulation, FPGA prototyping, and silicon. Read More

February 18, 2014
The Breker Trekker: Making Verification Debug Less Painful

Although Breker’s primary mission is uncovering RTL bugs, in practice users also find many errors in their verification models and in driver libraries called from the scenario models. Regardless of where the actual error occurred–hardware, software, or verification infrastructure–the detailed status provided by the TrekSoC/TrekSoC-Si log, the visualization of the runtime TrekBox display, and the tight interaction between the RTL simulation and the C test case all make debug much less painful. Read More

February 11, 2014
The Breker Trekker: Bugged about Debug? We Can Help!

We believe that the time has come to further automate SoC verification and to raise the level of abstraction for the models used. In our next blog post, we’ll provide some specific examples of how our graph-based scenario models, visualization technologies, and automatic test case generation reduce the number of errors in the verification infrastructure and reduce the time spent on all forms of debug. Read More

February 4, 2014
The Breker Trekker: More on the UVM: Processor or Verification Component?

Breker’s test cases run on bare metal and are designed to be efficient, so they will execute in simulation even when production code would be unacceptably slow. Any overhead incurred to keep the processors in the design is more than offset by faster and more thorough verification. Finally, the test cases are available early in the development process and can run on every platform: virtual prototypes, simulation, acceleration, emulation, FPGA prototypes, and even actual silicon in the lab. Read More

January 28, 2014
The Breker Trekker: We Like the UVM, Really We Do!

The UVM has limitations, and we address those with our tools and technologies. But the UVM forms a stable and standard base on which nearly all of our customers build their simulation-based verification environments. Read More

January 21, 2014
The Breker Trekker: Do Graph-Based Scenario Models Qualify as Formal?

The bottom line is that formal and graphs do have some overlapping terminology and technology, but are really addressing different aspects of the verification problem. Read More

January 14, 2014
The Breker Trekker: Guest Post: Formal Verification’s Perfect Storm of Change

In my opinion, not only will formal dominate verification, but my belief is that the effect of this technology will be as transformational as the advent of logic synthesis. Read More

January 7, 2014
The Breker Trekker: Can Graphs Make Modeling More Pleasant?

We have seen a strong positive customer response to our graph-based scenario models. Graphs are a natural way to express SoC functionality since they look very much like the dataflow diagrams that architects and designers draw to document the design and explain its functionality to others.   Read More

December 26, 2013
The Breker Trekker: Top 5 Holiday Gifts for the Verification Engineer

For about the same effort as hand-writing one simulation test case or one validation diagnostic, you can develop a vertically and horizontally reusable scenario model capable of generating hundreds or thousands of test cases and providing a summary of system coverage. Read More

December 17, 2013
The Breker Trekker: Memories … Light the Corners of My Verification Space

The automated solution provided by TrekSoC and TrekSoC-Si verifies memories thoroughly from system-level modeling through simulation, acceleration, emulation, FPGA prototypes, and even actual silicon. No other method verifies cache coherency, multiple address maps, and other advanced memory features nearly as well. Read More

December 10, 2013
The Breker Trekker: Who Will Win the Embedded Processor War?

We’ve worked very hard to remain processor-agnostic. When TrekSoC or TrekSoC-Si generates a test case, it produces the most generic C/C++ code that will do the job. The reason is simple: we want the same code to work with any embedded processor. As long as your processor has a C/C++ compiler, you’ll be able to compile and execute our test case. Read More

December 4, 2013
The Breker Trekker: Guest Post: Yes, Formal Will Dominate Verification

While “it’s tough to make predictions, especially about the future”, formal replacing most (but not all) of simulation is inevitable and the momentum is unstoppable. Read More

November 26, 2013
The Breker Trekker: Which Conferences Do Verification Engineers Like Best?

In EDA and electronics in general, a trade show is almost always accompanied by a technical conference. It’s surprising how much detail some vendors reveal about their products’ algorithms, so competitors can check each other out and potential customers can judge the technical capabilities of tools they might use. Read More

November 19, 2013
The Breker Trekker: Will Graph-Based Scenario Models Dominate Verification?

Graph-based scenario models scale vertically from IP to full SoC and horizontally from simulation through all forms of hardware platforms. If you’re not using them now, you’re missing out on the next big wave in verification. Read More

November 13, 2013
The Breker Trekker: Will Formal Really Dominate Verification?

I’m a big fan of formal, but I don’t think that I can comfortably predict that it will “dominate” verification. Let  me share my thoughts. Read More

November 4, 2013
The Breker Trekker: Emulation and Software-Driven SoC Verification: Two Peas in a Pod

SoC verification or software-driven verification tools provide a new set of tests to run on emulators. These tests bridge a gap between the simulation vectors and booting the O/S, increasing the value of emulation as a key hardware/software verification tool. I predict SoC verification will play a role in the continuing momentum of emulation. Read More

October 28, 2013
The Breker Trekker: Sneak Preview of this Week’s ARM TechCon in Santa Clara

In the world of EDA (and IP, and embedded systems), ARM is certainly one of the biggest recent success stories. As the company has grown, its small technical events have evolved into a major show now known as ARM TechCon. Breker will be both speaking and exhibiting at this week’s event in Santa Clara, just down the road from Breker’s headquarters in San Jose. Read More

October 21, 2013
The Breker Trekker: Guest Post: Documentation Is Not Just a Requirement

Documentation does take a team effort and everyone wins. It’s the questions that get asked, along with the followup discussions and answers, that make the documentation better, and the product better as well. Setting up a documentation process early can save a tremendous amount of time and effort, and results in improved documentation. Read More

October 15, 2013
The Breker Trekker: TrekSoC-Si: Achieving the Longstanding Goal of Horizontal Verification Reuse

We’ve expanded the Breker product line by adding TrekSoC-Si, a brand-new tool that generates multi-threaded, multi-processor, self-verifying C test cases for in-circuit emulation (ICE), FPGA-based prototypes, and actual production silicon. In other words, TrekSoC-Si does for hardware platforms what TrekSoC did for simulation.   Read More

October 8, 2013
The Breker Trekker: TrekSoC: Achieving the Longstanding Goal of Vertical Verification Reuse

Is there any form of verification component or verification IP that can be reused from IP block to subsystem to full SoC? Of course! The graph-based scenario models used by TrekSoC fit the requirements perfectly. Read More

October 1, 2013
The Breker Trekker: Hey, the EDA World Is Starting to Speak Breker’s Language!

It’s gratifying to see the industry not just taking notice but agreeing with us. If you like what others are saying about top-down verification, use cases, and scenarios, be sure and talk to Breker. As the old saying goes, we invented this stuff. Read More

September 24, 2013
The Breker Trekker: Let’s Coin a New Phrase: There Is no “I” in “Startup”

This is a play on the old saw that there is no “I” in “team” and the meaning is basically the same. No matter how great an athlete, in a team sport no individual can succeed without help from other players. Likewise, no CEO or founder can succeed without the rest of the company. As brilliant as Steve Jobs may have been, he was not an engineer and could not have produced the products he envisioned without a big team behind him. Read More

September 17, 2013
The Breker Trekker: Sneak Preview of the Upcoming SoC Conference in Irvine

If you look at the program, you’ll quickly see that this is one of the most diverse conferences of the year. A wide variety of experts from both academia and the commercial world considers SOC development from many different angles. One minute you may be listening to a talk on high-level system performance measurement, and the next on the silicon structures for a new type of on-chip memory array. Read More

September 10, 2013
The Breker Trekker: Two Peas in a Pod: Scenario Models and System Coverage

This example shows why scenario models and system coverage work so well together. The four realistic application scenarios appropriate for this digital camera fall out directly from the different paths through the model. One way to think about this approach is that the scenario model serves as the system specification and that system coverage can automatically be extracted from this model. Read More

September 3, 2013
The Breker Trekker: If the EDA Industry Has Zombies, What about Vampires?

It’s ideal if the startup can be bootstrapped or funded by “angel” investors in its early stages, perhaps turning to VCs later to fund growth. This increases the chances that the employees will own the majority of the company and not have to worry about a sudden takeover. Ideally, every investor should add some value to the company beyond just providing money. Read More

August 27, 2013
The Breker Trekker: An EDA Industry of Startups, Behemoths, Corner Stores, and Zombies?

It was part of my job to follow the EDA industry closely so that we could choose our tool investments based on both strength of technology and likelihood of vendor success. It seemed to me that the industry was divided into only three categories: major leaguers, minor leaguers, and startups. I observed that nearly all EDA startups disappeared after three or four years, with three possible endgames: acquisition, initial public offering (IPO), or bankruptcy. Read More

August 19, 2013
The Breker Trekker: If You’re Not Measuring System Coverage, Your SoC Is at Risk

True system coverage scales beyond functional coverage to measure whether all application scenarios, and all important variations on those scenarios, are exercised using self-verifying test cases. Even more important, any possible concurrent application scenarios must be verified. Read More

August 12, 2013
The Breker Trekker: Guest Post: A Look at DAC through Ray-Bans

Even Wednesday, the last day of the exhibition, was quite busy with visits from many senior-level managers. Our informal poll indicated that there are new design starts and the industry outlook is much like Austin’s weather during DAC: sunny and hot. Read More

August 5, 2013
The Breker Trekker: We Weren’t Kidding about Redefining “DAC” and “EDA”

My issue can be easily resolved by simply replacing “design” with “development” and “designer” with “developer” in any context involving the complete process of electronic product development. The nice thing about this proposal is that not a single acronym needs to change. EDA remains EDA, DAC remains DAC, EDAC remains EDAC, and so on. Many logos and URLs will be likewise unchanged. Read More

July 29, 2013
The Breker Trekker: Guest Post: A Journey from Nano-Scale SPICE Modeling to Giga-Scale SPICE Simulations at DAC

DAC proved we met our goal and was a memorable event. Our position that giga-scale SPICE simulation is an emerging need and DFY must be a complete and integrated solution to be effective has been heard. We’ll have even more to demonstrate at next year’s DAC in San Francisco! Read More

July 23, 2013
The Breker Trekker: Verification Beginning with the End in Mind

Folks who have been following Breker for a while know that we like the phrase “begin with the end in mind.” It succinctly summarizes why our use of graph-based scenario models is different than traditional constrained-random testbenches. Read More

July 16, 2013
The Breker Trekker: Alex, I’ll Take “SoC Verification” for $600

We studied the SoC verification problem deeply, looked at what was missing in existing approaches, and built our TrekSoC product to fill that gap. So of course we believe that SoC verification should be defined to match our solution. Four years of working with many of the largest SoC projects in the world have convinced us that we are on the right track. Read More

July 9, 2013
The Breker Trekker: Guest Post: OneSpin’s Successful Return to DAC

The conclusion we drew from this informal survey is that verification companies, including OneSpin, should make sure they cater to generalist engineers as well as verification specialists, and provide a broad range of offerings that match the spectrum of verification requirements across the industry. Read More

July 2, 2013
The Breker Trekker: Should EDA Still Have Its Head in the Cloud?

Specifically in the simulation domain, none of the major vendors has seen a push by customers to run in the cloud. The RTL source is considered too proprietary, and a compiled environment may be too large to transfer back and forth in reasonable time. Read More

June 18, 2013
The Breker Trekker: Raiders of the Lost Article

The lesson of social media is clear: assume anything online lives forever. The lesson is equally clear for content that you don’t want to lose: copy, don’t just bookmark and assume that it will be around forever. Read More

June 14, 2013
The Breker Trekker: Where, Oh Where Should My Little DAC Be?

No one really expected Austin to match San Francisco, but the numbers are quite respectable. What was especially interesting was that the number of exhibits-only passes exceeded by 15% those in San Diego in 2011. It seems that the local electronics community really turned out at DAC this year, already clear to us exhibitors since we saw many new faces we had not seen at shows in other locations. Read More

June 7, 2013
The Breker Trekker: Looking Back on DAC 2013

I can’t say enough good things about the decision to hold DAC in Austin. Our lead number speaks for itself and, as I noted in my last post, we saw a lot of local folks who had never attended a DAC before. We had tons of good food, including four of the most famous BBQ joints. Read More

June 4, 2013
The Breker Trekker: Check-In after Two Days at DAC 2013

In addition to seeing some old friends we’ve met many engineers from the Austin development centers we had not met before. Most said that they had never attended DAC in previous years but were glad to be able to do so in their own backyard. Read More

May 31, 2013
Dispatches from Boston: Breker Celebrates 10-Year Anniversary at 50th DAC

“Stitch and ship will sink a chip design” is almost a mantra within Breker and well worth exploring a bit more. Being verification experts, the Breker team has seen design teams mistakenly assume that an SoC full of multiple heterogeneous embedded processors will work as intended if individual IP blocks have been verified on their own. Read More

May 28, 2013
The Breker Trekker: A Matched Pair of Panels at DAC in Austin

The two verification panels above were carefully coordinated so that they address complementary aspects of the “crisis” in which verification is taking up an ever-larger percentage of chip and system development time. Read More

May 21, 2013
The Breker Trekker: Blog Post, Shall I Compare Thee to a Magazine’s Lifespan?

Although some recent posts have done a nice job of summarizing the strengths and weaknesses of print vs. online, they’ve missed the key point of retention. Once you have a physical publication, or an article clipped from one, you can keep it forever. Read More

May 7, 2013
The Breker Trekker: Come Celebrate DAC’s 50th Anniversary with Breker

Breker was founded in Austin and was headquartered there until moving to Silicon Valley two years ago. As one of the few EDA companies “born in Austin” we’re excited to return for this big show. Read More

May 2, 2013
The Breker Trekker: What Would Joe Say?

These facts don’t capture the almost mythical role that Joe Costello plays in the EDA industry.  I joined Cadence long after he had departed, but in my five years there I’ll bet I heard his name brought up nearly every week. His stint as the head of Cadence is inextricably intertwined with the glory days of the EDA industry. Read More

April 23, 2013
The Breker Trekker: Ladies and Gentlemen, Step Right Up!

In the EDA industry, most of the major conferences and tradeshows occur in the first half of the year, while most of the sales happen in the second. That’s not coincidental. New products are introduced at the events, users generally evaluate them in mid-year, and Purchasing departments usually want to close deals before the end of the calendar year. Read More

April 9, 2013
The Breker Trekker: And the Doctor Cried, “It’s a Blog!”

As we embark on this journey together, I’ll promise you three things. First, I will commit to a minimum of one new post every other Tuesday, with additional timely posts when major events occur. Second, I will do my best to make this blog interesting and worth reading. Finally, nothing reasonable will be off limits. Read More