September 10-11, 2015
Trek is an advanced graph-based constraint solver that develops functional verification tests for complex digital designs. Trek generates tests directly from a visual graph-based specification of verification requirements, making the entire process easy and systematic. Trek dramatically speeds verification coverage closure at the IP component level.
You can begin testing much earlier, even before RTL is finished, and then expand incrementally to get more complete coverage than you can with traditional testbenches. Trek’s intuitive graphical presentation lets you easily visualize the verification space and coverage closure. With Trek you can test more, in less time, with less effort.
Trek integrates easily into any verification flow: you don’t need to modify your existing testbench or learn a new language. Trek generates tests by traversing the scenario model graph. You can apply these tests to your design-under-test (DUT) in your normal simulation environment with no modifications to your testbench.
Trek is a natural way of implementing a test environment, with a knowledge-driven approach to directed tests and the flexibility of incorporating randomness into scenario generation and checking. Trek helps you develop a graph-based scenario model that describes your verification space, and then uses this model to automatically generate tests, including stimulus, expected results, and coverage.
With Trek, you create a scenario model that describes your verification space. Rather than forcing you to identify all possible inputs and create test cases, Trek lets you start by simply understanding the desired outcome and then defining the inputs that get you there. This outcome-oriented analysis ensures that you never forget a coverage objective.
You easily create models with minimal code using a combination of graphs and graph constraints. The models can be viewed in an intuitive graphical form, easy to share and review with colleagues. The graphical view highlights constraints and makes it easy to share and review verification information with your colleagues.
Pre-simulation reachability analysis shows graphically what can and cannot be tested, while post-simulation coverage analysis reveals gaps in your coverage. Simply click on an un-covered node and select “force” to generate additional tests and close the coverage gap. Trek can also automatically find a minimum set of tests to ensure that every node in the graph is covered.
All products in Breker’s Trek family include the Trek graph-based constraint solver. Within TrekSoC and TrekSoC-Si, Trek extends the power of IP component verification to verification of full system-on-chip (SoC) designs with one or more embedded processors. Trek is combined with generators that produce C code to run on the processors and transactions that run in UVM (or similar) testbenches. For chips without embedded processors, TrekUVM enhances existing transactional testbenches by using Trek to close coverage more quickly and predictably.
Trek is also available as a stand-alone product for custom application and integration into existing test-generation environments. For the first time, you have the power to quickly develop and reuse verification knowledge at all levels of the SoC design hierarchy. The same graph-based scenario models can be reused from the IP level to the SoC and system level.