Overview « Breker Verification Systems

February 26 - March 1, 2018
Booth # 304
Double Tree Hotel, San Jose, CA

Breker’s TrekSoC is the industry’s first, and most comprehensive, solution to the growing need for Portable Stimulus – to specify verification intent and behaviors that is reusable across target platforms such as Simulation, Emulation, FPGA, Silicon and Post-Silicon.

By deploying Breker’s suite of tools, customers have realized significant gains in getting to silicon faster for complex multi-core, multi-threaded, cache coherent system-on-chip (SoC) designs.  Practical, industry-proven solutions automatically generate C/C++ test cases for software-driven verification and auto-generated sequences for UVM testbenches.  Product portfolio also includes specific apps (“TrekApps“) for Cache Coherency, ARMv8 and Power Management Verification, that does not require any prior knowledge of Portable Stimulus Standard (PSS) graphs or scenario models to generate self-checking tests.

Since 2015, Breker has played a leading role in helping to define a Portable Test and Stimulus Specification through its active participation in Accellera’s Portable Stimulus Specification Working Group (“PSWG“).


The Graphic Truth about SoC Verification


The SoC Verification Iceberg

For the SoC with embedded processors and other bus agents sharing resources and interacting in unanticipated ways, verification of the individual IP components is not enough. Indeed, the top-level verification done by many SoC project teams is only the tip of the iceberg.


The SoC Verification Iceberg

Addressing the verification challenges beneath the surface requires robust test cases running on the embedded processors. It is too hard to exercise corner-case conditions using only an external testbench. Some SoC teams acknowledge this and develop manual tests to run on the processors. However, hand-writing code to run on multiple parallel, independent processors is in itself a major challenge. There is not enough time to understand, let alone verify, all possible system-level interactions.

The Breker SoC Verification Solution

The Breker TrekSoC and TrekSoC-Si products provide the solution to SoC verification challenges by automatically generating self-verifying C test cases for the embedded processors. These test cases exercise the corner cases of the design faster and more thoroughly than hand-written tests and trigger unusual conditions unlikely to occur even by running production code in the processors. TrekSoC generates test cases for architectural models, simulation, and acceleration, while TrekSoC-Si generates test cases for in-circuit emulation, FPGA-based prototypes, and production silicon. The same scenario models are used for generation across all  these platforms.

Solution for Platforms

In production use, Breker’s suite of tools address all of the major challenges faced by verification teams using traditional methods:

  • Manual development of test cases: TrekSoC and TrekSoC-Si are fully automated, generating compiled C test cases that run in your SoC’s embedded processors
  • Limited time and memory: full-chip simulation is often slow and SoCs have limited memory, but the test cases generated by TrekSoC and TrekSoC-Si make efficient use of both time and memory
  • Difficulty controlling testbench actions: it is hard to coordinate corner cases from the testbench along; TrekSoC and TrekSoC-Si use the power of the embedded processors to verify your chip while controlling the input and outputs via bus functional models (BFMs) without the need of a testbench
  • Need to support multiple environments: TrekSoC and TrekSoC-Si can integrate into multiple simulation environments as well as simulation acceleration, emulation and prototypes, with the generated C tests running in all these environments as well as in the final SoC
  • Limited reuse of test cases: in addition to portability across multiple environments, the TrekSoC and TrekSoC-Si test cases can be reused from the IP block level all the way to your full chip or full system
  • Lack of high-level coverage models: TrekSoC and TrekSoC-Si supplements the familiar low-level simulation coverage metrics with a scenario-based system-level coverage view that better represents system behavior and supports a more sophisticated SoC verification plan

TrekSoC and TrekSoC-Si provide a set of verification services that help you build high-level scenario models to describe the SoC’s operation. TrekSoC and TrekSoC-Si use these models to build a graph-based representation that the Trek constraint solver can use to generate the test cases. TrekSoC and TrekSoC-Si provide fast, efficient verification that catches corner-case bugs before silicon, decreasing your time to market and increasing the quality of the SoC and the end products containing it. The end result is increased profitability.