News & Events
Press Releases
Breker Verification Systems Celebrates 10-Year Anniversary
Breker Verification Systems will celebrate its 10th anniversary now through the 50th Design Automation Conference (DAC), where it will exhibit in Booth #2015 June 3-5 at the Austin Convention Center in Austin, Texas. Crowning 10 years of achievement is TrekSoC, Breker's flagship software that automatically generates self-verifying and synchronized C test cases to run on an SoC's multiple heterogeneous embedded processors for faster and more thorough verification. Read more
Breker Verification Systems to Exhibit at SNUG Silicon Valley Designer Expo
Breker Verification Systems Will exhibit at SNUG (Synopsys Users Group) Silicon Valley Designer Community Expo Booth #102 in the IC Verification community, open to all registered attendees of SNUG Silicon Valley. Breker will demonstrate TrekSoC, software that automatically generates self-verifying and synchronized C test cases to run on an SoC's multiple heterogeneous embedded processors for faster and more thorough verification. Read more
Breker Verification Systems to Sponsor Verification Futures India
Breker Verification Systems and Indian distributor CMR Design Automation P Ltd. Will demonstrate TrekSoC, software that automatically generates self-verifying and synchronized C test cases to run on an SoC's multiple heterogeneous embedded processors for faster and more thorough verification, at Verification Futures India 2013, an event for senior verification engineers and managers. Read more
Breker Verification Systems to Demonstrate Its SoC Verification Software at CDNLive Silicon Valley
Breker Verification Systems, The System-on-Chip (SoC) Verification Company, Will demonstrate TrekSoC, software that automatically generates self-verifying and synchronized C test cases to run on an SoC's multiple heterogeneous embedded processors for faster and more thorough verification, at CDNLive Silicon Valley, the Cadence User Group, in Booth #E3. Read more
Breker Verification Systems to Host Breakfast Panel During DVCon 2013
Breker Verification Systems will host a breakfast and panel discussion titled, "How Does Anyone Tape Out Working Chips Anymore?," and moderated by Brian Bailey, editor of EE Times' EDA DesignLine, during DVCon 2013. The breakfast event will be held Tuesday, February 26, from 7:00 to 8:15 a.m. Read more
Breker Verification Systems Enhances TrekSoC GUI
Breker Verification Systems, The System-on-Chip (SoC) Verification Company, today unveiled an enhanced graphical user interface (GUI) for TrekSoC, software that automatically generates self-verifying and synchronized C test cases to run on an SoC's multiple heterogeneous embedded processors for faster and more thorough verification. Read more
Breker Verification Systems' Tom Anderson to Present "Cracking the Challenge of SoC Low-Power Verification" During DesignCon 2013
Thomas L. Anderson, vice president of marketing at Breker Verification Systems, The System-on-Chip (SoC) Verification Company, will offer a look at "Cracking the Challenge of SoC Low-Power Verification" during DesignCon on Wednesday, January 30, at 10:15 a.m at the Santa Clara Convention Center, Santa Clara, Calif. Read more
Breker Verification Systems' Thomas L. Anderson to Participate in Panel at Microprocessor Test and Verification 2012
Thomas L. Anderson, vice president of marketing at Breker Verification Systems, the System-on-Chip (SoC) Verification Company, will participate in a panel titled, "My IP Works. Go ahead -- Use it to Build Your SoC: Verification Challenges with High-Use Design IP," during the workshop on Microprocessor Test and Verification (MTV 2012) on Tuesday, December 11 at 10 a.m. Hyatt Regency in Austin, Texas Read more
Breker Verification Systems to Sponsor Verification Futures 2012
Breker Verification Systems, the System-on-Chip (SoC) Verification Company, will sponsor the three-day European Verification Futures 2012 and showcase the latest release of TrekSoC, software to solve complex verification challenges for SoC designs containing multiple embedded processors by automatically generating self-verifying C tests. Read more
Breker Verification Systems to Exhibit at ARM TechCon 2012
Breker Verification Systems, the System-on-Chip (SoC) Verification Company, will exhibit at ARM TechCon 2012 in Booth #TT30. It will feature the latest release of TrekSoC, software to solve complex verification challenges for SoC designs containing embedded processors by automatically generating self-verifying C tests. New capabilities offer support for designs with multiple heterogeneous embedded processors. Read more
Breker Verification Systems Adds Support for Multi-Processor SoCs
Breker Verification Systems, the system-on-chip (SoC) Verification Company, today announced that the latest release of its TrekSoC software supports SoC designs that include multiple heterogeneous embedded processors. TrekSoC automatically generates self-verifying C test cases that run on the SoC's processors in a fully synchronized manner for faster and more thorough verification. Read more
Breker Verification Systems to Present "SoC Verification from the Inside Out" at SoC Conference
Thomas L. Anderson, vice president of marketing for Breker Verification Systems, the System-on-Chip (SoC) Verification Company, will present "SoC Verification from the Inside Out" at the 10th International SoC Conference on Thursday, October 25, at 2:10 p.m. at the Hilton Irvine/Orange County Airport, Irvine, Calif. Read more
Breker Verification Systems Appoints CMR Design Automation P Ltd. as Exclusive Distributor in India, Singapore
Breker Verification Systems, The SoC Verification Company, today announced it signed CMR Design Automation P Ltd. to a multi-year agreement as its exclusive distributor in India and Singapore. CMR Design Automation P Ltd., one of India's most experienced and successful Electronic Design Automation (EDA) solutions suppliers, brings to design teams in India and South Asia cutting-edge technologies from focused EDA companies as quickly as possible. Read more
Breker Verification Systems Secures $5 Million in Funding
Breker Verification Systems, The SoC Verification Company, today announced that it has raised $5 million in Series A funding. Funding was provided by Astor Capital Group, a private equity fund out of Far East Asia. Funds will be used as working capital to scale Breker's operations, expanding in all areas of sales, support and research and development. Read more
News Coverage
McCombs Today: How To Live With An Entrepreneur
"When you are starting a company, there is a lot that needs paying attention to," Adnan says. "She knew business from her family and knew how to handle the bumps and the ups and the downs." Read more
EDA DesignLine: What were they thinking: stimulus coverage
The only way I know how to do this is based on tracking backwards through the design, just like the old tester methods used to do. Those methods proved too compute intensive at the gate level and the patterns generated were too long as design sizes grew and so alternative methods were found, but for functional verification it is what needs to happen. Formal methods attempt to do this as does the graph-based approach being developed by Breker Verification Systems. Read more
Chip Design System-Level Design Community: Experts at the Table: Verification Strategies (Part 3)
When it comes to some of these new orthogonal areas like CDC and power, if you get it wrong you're generally dead. With low-power bugs, you basically throw away the chip. If you power down some piece of a chip and it doesn’t come back up, what do you do? Read more
Chip Design System-Level Design Community: Experts at the Table: Verification Strategies (Part 2)
There's a lot of trust and a lot of history with companies that have been in the IP business for 15 years. They’ve produced thousands of chips that work. So people are less concerned about re-verification. But the effective re-use of any piece of a verification environment for an IP block is not very well done yet. Read more
EDA Cafe: Interview with Tom Anderson, Breker V.P. of Marketing
It's really a way of verifying the SoC from the inside out. People think of testbenches primarily for verification, where you're trying to verify the chip from the outside in. You're trying to engage deep behaviors in the chip purely through the I/O ports. That's hard to do on a big chip. Read more
Chip Design System-Level Design Community: Experts at the Table: Verification Strategies (Part 1)
Because most of the chips out there are SoCs with embedded processors, you need to use the embedded processors to help verify the chip. It's either an automated approach, or just hand-written tests or diagnostics that run simulation/emulation on those embedded processors. The approach is verification from the inside out. Read more
Chip Design System-Level Design Community: Verifying Complex Chips
They do need to take advantage of the embedded processors that are within the SoCs to help verify the SoCs from the inside out. After all, if the SoC is doing its job in the final application, it's the embedded processors that are in charge. So it just makes sense to leverage the power of those embedded processors as part of the verification process. Read more
Electronic Engineering Times: Anyone for a Free Breakfast Next Week?
I will be moderating a breakfast panel on Tuesday morning 7:00am to 8:15am in the San Carlos/San Juan room at the Doubletree. Its title - How Does Anyone Tape Out Working Chips Anymore? This panel is being organized by Breker Verification, an exhibitor at the conference. Read more
Electronic Engineering Times: EDA/IP Weekly Roundup – February 20th 2013
TrekSoC produces multiple streams of real-world user scenarios and schedules the steps so that they cross threads and processors. Since these intertwined test cases are hard to follow, the new GUI features show clearly how the streams are scheduled across threads and how each is making progress in simulation Read more
VerificationOnWeb: Dare to Think beyond UVM for SoC Verification
UVM is serving the very purpose it has been developed for – to create interoperable, reusable VIPs. However a full SoC verification is much more than a bunch of VIPs. It requires next abstraction level models such as the graph based scenario models. Such scenario models can then be compiled by TrekSoC to produce C-tests and/or UVM transactions. Read more
EDACafe: Breker: Anderson's Verification Tutorial Rocks DesignCon
One of the most widely used low-power design techniques is power shutoff (PSO), a choice that can have the biggest impact on functional verification. Turning off the power completely to unused logic regions called "power domains" saves both dynamic and static leakage power. The outputs of such un-powered domains must be held in isolation from the rest of the chip, and often there is critical state that must be saved and restored. Read more
Electronic Engineering Times: Predictions for 2013 - EDA/IP
A solution known as graph-based scenario models that capture intended behavior of the IP blocks is emerging. 2013 will see broad adoption of this approach, verifying the complete SoC while finally providing a level of verification reuse matching that of design reuse. Read more
Electronic Engineering Times: Stars of DesignCon: Inside-Out Test Verifies Low-Power SoCs
Our new technique uses test cases to verify the SoC from the inside out, rather than from outside-in as with normal test-bench techniques. And when an error is detected, the engineer can step-through the particular failed test case to see where it breaks down. Read more
EDN: A Sneak Peek into DesignCon
Although simple in concept, the verification of SoCs using power shutoff is a significant challenge. This paper looks at a technique that generates self-verifying C test cases that run on the embedded processors in simulation and exercise a wide range of functionality while turning the power domains off and on. Read more
Chip Design System-Level Design Community: Experts at the Table: SoC Verification (Part 3)
In some cases we are taping these things out without fully verifying them, and then we’re taking the hit in the software arena. The problem is functionality and performance over time because of all the bugs in the hardware. All of the big companies are looking at why it takes so long to get the software working. It's because there are bugs in the chip and it takes so long to find them and work around them. Read more
Electronic Engineering Times: A Look Back on 2012 - Verification
An ongoing trend comes from the consumer electronics market segment driving the creation of SoCs with multiple embedded processors for enhanced product functionality and performance. In 2012, Breker announced support for these types of SoC designs –– a major accomplishment. TrekSoC automatically generates multi-threaded test cases for SoC designs with multiple heterogeneous embedded processors, providing effective verification between stitching and shipping. Read more
Chip Design System-Level Design Community: Experts at the Table: SoC Verification (Part 2)
The integration guys have to tape out. They don’t get the opportunity to wait. They know they’re doing a quarter to 10% of the verification they want to do, and where they get hit is in the validation when the chip comes back. The software guys take the hit because the bugs in the chip take a very long time to find and debug—or worse, the chipmaker’s customer finds it, which takes even longer to debug. Read more
Electronic Engineering Times: A Look Back on 2012: Industry Observations
The biggest surprise of 2012 was the surprise many SoC design teams received when they realized stitch and ship doesn’t work. This optimistic verification process will sink them every time because they’ve failed to exercise a wide range of functional scenarios. A common misperception is that the SoC will work as intended if the IP blocks on the chip have been well verified. In fact, scenarios that represent user applications and measure performance can only be run at the full-chip level. Read more
Chip Design System-Level Design Community: Experts at the Table: SoC Verification (Part 1)
We're starting to re-use design components in designs, but we have no idea how to do that for verification or test cases. How do you do plug-and-play verification so you can take information from the IP guy, plug it into an environment that works with the subsystem or system or software and each person along that chain gets to use information from the person downstream from him. This is all about knowledge transfer. Read more
Chip Design System-Level Design Community: The Growing Verification Challenge
We are far from being done with demanding more capabilities integrated into smaller chips with more features. The chip doesn't matter, only the product matters, and something only works if it's been tested. Those who can verify will survive; those who can't will die. Read more
Press Contact: Nanette Collins nanette@nvc.com
