Case Studies « Breker Verification Systems
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September 14 - 15, 2017
Booth # 404
The Leela Palace, Bangalore, India
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cavium

“Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” See More

Presentation and Paper, Design and Verification Conference (DVCon), 2015

altera

“Verification of a Cache Coherent System with an A53 Cluster Using ACE VIP with Graph Based Stimulus” See More

Presentation, Microprocessor Test and Verification (MTV) Workshop, 2015

altera

“Verification of a Cache Coherent System with an A53 Cluster Using ACE VIP with Graph Based Stimulus” See More

Presentation, Synopsys Users Group (SNUG) Austin, 2015

ibm

“Walking the Graph: A Holistic Approach to Graph-Based Verification for Logic with Sparse State Space” See More

Presentation, Design and Verification Conference (DVCon) India, 2015

verifworks

“Coverage Closure – Is it a ‘Game of Dice’ or ‘Top 10 Tests’ or ‘Automated closure’?” See More

Presentation, Design and Verification Conference (DVCon) India, 2015

altera

“SoC FPGA: What a Monster!” See More

Lunchtime Seminar, Design Automation Conference (DAC), 2015

ibm

“Walking the Graph: A Holistic Approach to Graph-Based Verification for Logic with Sparse State Space” See More

Presentation, Design Automaton Conference (DAC), 2015

broadcom

“How Does Anyone Tape Out Working Chips Anymore?” See More

Breakfast Panel, Design and Verification Conference (DVCon), 2013

ibm

“Graph-Based Verification Patterns” See More

User Track Poster, Design Automation Conference (DAC), 2013

nvidia

“A Trek Testimonial” See More

Video Interview, YouTube, 2011

st

“Test Generation – Perceived Value and Application” See More

Presentation, European DVClub Event, 2012

st

“Graph-IC Verification” See More

Paper, Design and Verification Conference (DAC), 2012