Press Coverage « Breker Verification Systems

February 26 - March 1, 2018
Booth # 304
Double Tree Hotel, San Jose, CA

May 29, 2017
Semiconductor Engineering: Verification Cowboys

What does it take to be a successful EDA startup? Seven verification company executives provide some insight. Read More

May 25, 2017
Semiconductor Engineering: Respecting Reset

Reset is one of the most important signals in a design and yet perhaps one of the least respected. What can go wrong and how to correct it. Read More

May 11, 2017
Semiconductor Engineering: Closing The Loop On Power Optimization

Minimizing power consumption for a given amount of work is a complex problem that spans many aspects of the design flow. How close can we get to achieving the optimum? Read More

March 29, 2017
Semiconductor Engineering: Custom Chip Verification Issues Grow

No simple solutions to deal with market-specific requirements and advanced process node issues. Read More

March 23, 2017
Semiconductor Engineering: Users Talk Back On Standards Process

How does a standard get created? A lot of hard work and balancing different opinions can be frustrating, but that communication is vital. Read More

March 23, 2017
Chip Design: Portable Stimulus

Portable Stimulus (PS) is not a new sex toy, and is not an Executable Specification either.  So what is it?  It is a method, or rather it will be once the work is finished to define inputs independently from the verification tool used. Read More

February 23, 2017
Tech Design Forum: Cache-coherency checks call on portable stimulus

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects. Read More

February 15, 2017
Tech Design Forum: DVCon US 2017 preview: Mentor Graphics

Creating Portable Stimulus Models with the Upcoming Accellera Standard (February 27th, 9:00am - 12:00pm, Rm: Oak) sees the company join representatives from fellow EDA vendors Breker Verification Systems, Cadence Design Systems and Synopsys, as well as Analog Devices, Intel and Vayavya Labs. The session will preview the main features of the new standard for portable testbench components and provide some coding demonstrations of its capabilities. Read More

February 3, 2017
Semiconductor Engineering: Uncovering Unintended Behavior

First of two parts. Does your design contain a Trojan? Most people would never know, and do not have the ability to find the answer. Portable Stimulus (PS) is a new verification methodology based on a verification intent model that may see a lot of development in 2017. “PS is a graph of all behaviors,” explains Adnan Hamid, chief executive officer of Breker Verification Systems. Read More

January 31, 2017
Embedded Computing Design: Portable Stimulus - System-level Verification Trends for 2017 and Beyond

The functional space has had more innovation than any other part of the front-end design flow, and yet the amount of time and effort spent in verification continues to grow. The problem stems from rising complexity and the fact that simulation as a technology has failed to scale ever since single processors stopped becoming more powerful. It is compounded by an increasing number of tasks that verification is expected to perform, such as power verification. Read More

December 8, 2016
Semiconductor Engineering: Reflecting Back On 2016: Markets

How last year’s predictions panned out over the past 12 months. Read More

November 10, 2016
Semiconductor Engineering: Toward Real-World Power Analysis

Emulation adds new capabilities that were not possible with simulation.  Portable Stimulus will drive a piece of it. Read More

October 27, 2016
Semiconductor Engineering: Emulation's Footprint Grows

Why emulators are suddenly indispensable to a growing number of companies, and what comes next. Read More

October 17, 2016
Tech Design Forum: Portable Stimulus Gears Up To Accelerate Verification

Interview of Breker CEO Adnan Hamid on the topic of Portable Stimulus by Chris Edwards of Tech Design Forum   Read More

October 12, 2016
Semiconductor Engineering: Rethinking Verification For Cars

Second of two parts: Why economies of scale don't work in safety-critical markets. Read More

September 29, 2016
Semiconductor Engineering: Gaps In The Verification Flow

Experts at the Table, part 1: The verification task is changing and tools are struggling to keep up with them and the increases in complexity.  More verification reuse is required. Read More

July 28, 2016
SemiconductorEngineering: What’s Next For UVM?

Both users and vendors are critical for the development and evolution of effective standards. The users understand the problems they are trying to solve and are on guard against solutions proposed just because they might be convenient for the vendors to implement. On the flip side, the vendors serve as a reality check that proposed standards can be implemented. Read More

June 15, 2016
SemiconductorEngineering: System-Level Verification Tackles New Role, Part 3

Thinking that you can always fix it in software may lead to a lack of focus on quality. If you’re talking about a self-driving car or an implanted medical device, that’s a scary prospect. Moving functionality from hardware to software should not be an excuse to do less verification. Read More

June 9, 2016
SemiconductorEngineering: System-Level Verification Tackles New Role, Part 2

The portable stimulus approach holds the promise of a single model to define verification intent, from which you can generate test cases for various platforms. IP vendors can provide models that you can plug together for full-chip verification. Read More

May 18, 2016
SemiconductorEngineering: Bridging the IP Divide

Graph-based models that support portable stimulus are very helpful in fulfilling the need for a more formal definition of intent. They provide a common method for all IP vendors and IP users to document verification intent and enable reuse from block to chip to system, and from simulation to silicon. The flexibility of graphs means that it is easier for an IP vendor or IP user to adapt the verification environment as IP blocks are configured or customized. Read More

April 28, 2016
SemiconductorEngineering: Experts at the Table: System-Level Verification Tackles New Role, Part 1

If you can generate very dense test cases that exercise multi-IP scenarios in parallel while keeping all the processors, I/O channels, and memories really busy, then you can get a realistic approximation of performance. You can’t write these sorts of tests by hand. You have to generate them for multiple platforms using portable stimulus techniques. Read More

April 28, 2016
SemiconductorEngineering: ESL Flow Is Dead

One emerging area is a new verification methodology based on graphs. This not only provides a new verification abstraction, but finds a way to tie it into the existing methodologies. “Accellera has the Portable Stimulus Working Group that is tied to the ESL problem,” says Adnan Hamid, chief executive officer of Breker Verification Systems. “It is trying to define the verification intent once and then able to use this throughout the flow going down to implementation and then back up through integration.” Read More

January 28, 2016
SemiconductorEngineering: Predictions For 2016: Tools and Flows

Accellera’s Portable Stimulus Working Group (PSWG) will release a standard defining a single abstract, graph-based specification that can be used to automatically generate test cases (stimulus, results, and coverage) for multiple verification environments and platforms. These test cases will be tuned for efficient execution in each target, ensuring “vertical” portability from IP block to system-on-chip (SoC) and “horizontal” portability from simulation through emulation and FPGA prototyping to actual silicon in the lab. Read More

January 21, 2016
SemiconductorEngineering: Predictions For 2016: Semiconductors, Manufacturing And Design

Chips produced for IoT applications will be more complex that many people expect." Driven by the need for better security and multiple communications methods, processing power will need to be greater than what a low-end microcontroller can provide. In order to keep power consumption as low as possible, multi-CPU designs will be preferred over a single high-performance processor. Read More

December 10, 2015
Semiconductor Engineering: Reflections On 2015

Many SoCs with several or even dozens of processors [have] been announced, nearly all with multi-level caches. Many of the IP vendors supplying interconnect buses and fabrics released cache-coherent versions this year. One result is that coherency verification is now the problem of the SoC integrators, not just CPU designers. Read More

November 12, 2015
SemiconductorEngineering: One Flow To Rule Them All

The [PSWG] standard is still under development and the exact specification format is under discussion, but it is clear that a graph-based scenario model of the verification space provides the necessary level of abstraction. From this one model, EDA tools can generate test cases appropriate for verifying ESL and HLS models in virtual platforms, RTL models in simulation, gate-level models in simulation, acceleration, emulation, and FPGA prototypes, and even fabricated silicon in the lab. Read More

July 30, 2015
SemiconductorEngineering: IP Verification Challenges

One of those panels was titled Key Challenges of Verification and Validation of Modern Semiconductor IP and panelists included Tom Anderson, vice president of marketing for Breker Verification Systems. Read More

May 1, 2015
VerifNews: Cache Coherency Verification automated – TrekApp @ DVClub Europe

As part of our continued coverage of various DV events across the globe, here we present a detailed account of a great, in-depth technical presentation delivered by Adnan Hamid, Co-Founder and CTO of Breker Verification Systems, Inc. Adnan presented on the title “Cache Coherency Verification with Vertical and Horizontal Portable Stimulus” at DVClub Europe 2015. Read More

April 23, 2015
VerifNews: Cache Coherency Verification with Portable Stimulus – from DVClub Europe

Adnan briefly discussed about need of Cache Coherency Verification at every target platform whether it is Simulation, Emulation, Prototyping or Post Silicon (Hence the idea of “Portable Stimulus”). Cache Coherency Verification is also frequently required at all levels of abstraction, be it SoC, Subsystem or Unit. Point to note here is that, SoC verification is basically done using software driven methods, whereas verification at subsystem & unit levels is transactional. Read More

February 11, 2015
Accellera: Accellera Systems Initiative Forms Portable Stimulus Working Group - Quote sheet

It was clear from our active participation in the Proposed Working Group that the industry has a strong desire for portable stimulus and tests, including checks and coverage. As a pioneer in this space, Breker has joined Accellera and we are eager to help lead the Working Group to a solution that is portable from IP to full system and from simulation to silicon.   Read More

February 10, 2015
SemiconductorEngineering: Experts at the Table: Software-Driven Verification, Part 3

There is a solution out there that works today for automating the generating of C tests that is scalable. I think there is evidence that it is accelerating with increasing adoption and more vendors are offering solutions in this space. We don’t see the lack of a standard as a hindrance, but it is likely that in a year or two years from now, software-driven verification is likely to become a fairly standard methodology. Read More

January 29, 2015
SemiconductorEngineering: Tools And Flows In 2015

The ongoing move toward portable tests, driven in part by the Accellera Portable Stimulus Working Group, is an example of users demanding that verification solutions be portable "vertically" from block to SoC and "horizontally" from simulation through emulation and FPGA prototyping to actual silicon in the lab. Read More

January 15, 2015
SemiconductorEngineering: What Will Change In Design For 2015?

There is a clear trend that the system on chip (SoC) with one processor is moving to multiple processors with cache coherency. Coherency will be required beyond the CPU clusters, as GPUs, DMA engines, application processors, and I/O devices will all have to be coherent to some extent. Three-level caches will dominate, and all on-chip buses, interconnects, and all on-chip buses, interconnects, and on-chip networks will support cache coherency. Read More

January 5, 2015
SemiconductorEngineering: Experts at the Table: Software-Driven Verification, Part 2

If you are just testing your hardware with one version of your software, your coverage is not good. And when the next version comes out, the software doesn’t work anymore. So the whole idea that you have some orthogonality to that particular piece of production software and the ability to go and manipulate the design which is orthogonal to the view the OS provides is very important. Read More

December 30, 2014
SemiWiki: SoCs Should Invest in a Strong Cache Position

Breker and Carbon have teamed up for one solution, using automatically generated test cases against a virtual prototype with 100% accurate models. This allows a robust set of test cases to execute cache stress tests against known-good IP block models in a system-level configuration. Read More

December 22, 2014
SemiconductorEngineering: Industry Scorecard For 2014

The world is clearly moving away from the UVM for full-chip simulation. In fact, in mid-year the Accellera standards body formed a proposed working group to look beyond the UVM for solutions to “portable stimulus” reusable both vertically from IP to system and horizontally from simulation to silicon. Read More

December 18, 2014
SemiconductorEngineering: Experts at the Table: Software-Driven Verification, Part 1

Software-driven verification could be viewed as UVM++. It is the processor that changed everything. UVM works great until you add the processor and UVM has no notion of processor, software running on a processor or communications between software and the testbench. None of that exists in UVM. Read More

December 4, 2014
SemiconductorEngineering: An Architectural Choice Overdue For Change

The availability of cache-coherent multiprocessor clusters in FPGAs has enabled a whole new generation of designs without the cost and fabrication time of custom chips. Read More

December 4, 2014
SemiconductorEngineering: Problems Lurk In SoC Boundaries

Formal analysis is very effective at proving that a power controller meet its specs and makes all transitions properly. But only running realistic use cases while power is changing can verify that the chip’s functionality is unaffected. Read More

September 25, 2014
SemiconductorEngineering: How To Cut Verification Costs For IoT

One of the reasons that there are so many verification steps today is that there is limited opportunity for verification reuse, both ‘vertically’ from block to subsystem to full chip, and ‘horizontally’ from ESL and RTL simulation to hardware platforms to silicon. Read More

August 13, 2014
SemiconductorEngineering: Newer Processes Raise ESL Issues

Simple tests do not validate the chip well, and many companies are seeing returns with defects missed by the tester. Test time limitations typically prohibit the download and run of an operating system and user applications, but clearly a better test is needed. The answer is available today: automatically generated C test cases that run on “bare metal” (no operating system) while stressing every aspect of the SoC. Read More

May 22, 2014
SemiconductorEngineering: Executive Insight: Adnan Hamid

What is keeping my customers up at night is trying to get products out of the door, getting them right and that means verification. They know they are behind and they need to do something different. What keeps me up at night is finding out ways to get them to switch over to a new paradigm. I need to get them to stop using a few directed tests and instead use program generation for system testing.   Read More

May 13, 2014
Chip Design: IP Integration: Not a Simple Operation

Thomas L. Anderson, VP of Marketing at Breker Verification Systems pleads: integrate, but verify.  He argues that “The truth is that most SoC teams trust integration too much and verify too little. Many SoC products hit the market only after two or three iterations through the foundry. This costs a lot of money and risks losing market windows to competitors." Read More

May 5, 2014
EDACafe: Asymptotic or Divergent: Three Verification Managers Look to the Future at DAC

Proposed and organized by Graham Bell of Real Intent, users make up the panel and include Brian Hunter of Cavium, Holger Busch at Infineon Technologies and Bill Steinmetz from NVIDIA. Special thanks go to Breker, OneSpin and Real Intent for securing these three experts who will share their real-world experiences with formal verification, static RTL analysis, and graph-based verification. Oh yes, they are users of Breker, OneSpin and Real Intent tools.   Read More

April 24, 2014
SemiconductorEngineering: Graphing Toward Standardization

Graph-based scenario models are extensible in two dimensions. They enable IP-to-system vertical reuse, since any graphs developed for individual IP blocks can be directly instantiated into higher-level design blocks all the way up to the full-chip level. This provides much more reuse than testbenches, since UVM Verification Components (UVCs) and other testbench elements cannot simply be combined as the verification moved upward. Scenario models are also horizontally re-used across the course of an SoC project. The same model can automatically generate test cases for virtual prototypes, RTL simulation, simulation acceleration, in-circuit emulation (ICE), FPGA prototypes, and actual SoC silicon in the bring-up lab. Read More

April 11, 2014
Chip Design: Internet of Things (IoT) and EDA

A better approach is a bulletproof SoC whose hardware, software, and combination of the two have been thoroughly verified. This means that the SoC verification team must anticipate, and test for, every possible user scenario that could occur once the node is in operation. Read More

March 31, 2014
SemiconductorEngineering: Experts at the Table: Big Shift In SoC Verification, Part 3

The embedded engineers who are on loan have to learn something about RTL and simulation. At the same time, some knowledge is going to rub off on the verification team about embedded software. It may not be a new breed of engineer, but there is a hybrid skill set occurring as a result of this cooperation. Read More

March 27, 2014
SemiconductorEngineering: EDA Shapes Its Future

Although some embedded systems suppliers are nibbling at the edges of EDA, it is more likely that the major EDA companies will be the acquirers. They already span the complete SoC development process, so adding in more of the software components will be relatively painless on the technical side.   Read More

March 27, 2014
SemiconductorEngineering: Biggest Verification Mistakes

The biggest issue we see with SoCs is people assuming just because they’ve done a good job verifying the individual blocks, you just sort of plug them together and expect them to work. We had an early customer that had a big SoC – a processor and a whole bunch of different blocks – and they had actually done a pretty good job of verifying that the blocks were integrated correctly. What they never did was stream the blocks together into what we call a user scenario.   Read More

March 20, 2014
SemiconductorEngineering: Enabling Test Portability With Graphs

If you are running a handwritten diagnostic test in hardware, let’s say, in the bring up lab, it’s usually very hard to port that back to simulation. At the same time it’s really impossible to take simulation-based vectors and port them to hardware because you no longer have direct access to the I/O ports. Read More

March 17, 2014
SemiconductorEngineering: Experts at the Table: Big Shift In SoC Verification, Part 2

A lot of us have experience in different representations of the system level that enable descriptions of how the IP blocks are connected and how things are put together in real user scenarios. Graph-based verification is something we have experience with. We found a common language between the architect, the validation teams, the embedded guys and the hardware guys. Read More

March 6, 2014
SemiconductorEngineering: Experts at the Table: Big Shift In SoC Verification, Part 1

The shift we’ve seen in the past two years is that people are no longer relying exclusively on a test bench, UVM or otherwise, at the full-chip level if they have an SoC with processors involved. They’re either manually writing or internally generating or using a commercial product to generate tests to run those processors and do a lot of the verification. Read More

February 27, 2014
SemiconductorEngineering: 10 Must Knows About Virtual Prototypes

The best hope for unifying the virtual prototype is with a model suitable for high-level synthesis (HLS). Today, although both models are often written in SystemC, they tend to be quite different. It’s a hard problem to unify them, and many argue that it cannot be done. Read More

February 27, 2014
SemiconductorEngineering: EDA Hungers For Growth

The EDA industry has done a surprisingly good job of acquiring IP and establishing a separate business model from EDA tools. For the most part, EDA companies have been able to keep IP out of the ‘all-you-can-eat’ deals that have done so much damage to the industry.   Read More

February 21, 2014
Electronic Engineering Journal: Amelia's Weekly Fish Fry Interview with Tom Anderson

As soon as you move to a hardware platform--in-circuit emulation, FPGA prototyping, or the actual silicon--you no longer have easy access to the I/O pins. So what you really want to do then is have a program that's optimized on running  internal tests in the chip, and running many more of them because of course the speed is so much faster. So that's where TrekSoC-Si comes in. Read More

February 13, 2014
SemiconductorEngineering: Do Chips Really Work The First Time?

The high cost and product schedule impact on a chip turn mean that design teams will invest a huge amount of effort trying to find a software workaround for every hardware bug found post-silicon. Read More

February 11, 2014
Chip Design: Verification Management

Coverage is, frankly, all that the verification team has to assess how well the chip has been exercised. Code coverage is a given, but in recent years, functional coverage has gained much more prominence. The most recent forms of coverage are derived automatically, for example, from assertions or graph-based scenario models, and so provide much return for little investment. Read More

January 30, 2014
SemiconductorEngineering: The Road Ahead For 2014: Tools

We expect an abandonment of the Universal Verification Methodology (UVM) for system-on-chip (SoC) simulation. While the UVM has proven effective for IP blocks and subsystems, its limited vertical reuse and lack of links to embedded processors make it impractical for significant full-chip simulation. Read More

January 16, 2014
SemiconductorEngineering: Performance Still Trumps Power

Some SoCs have more than 100 power domains. The tradeoff for this flexibility is much more complexity in the design and verification process. Read More

December 23, 2013
Electronic Engineering Journal: The Year in EDA: Did Anything Happen?

Companies are trying to standardize on as few hardware platforms as possible. They then use software to differentiate. That brings in a whole new set of headaches. Breker, of course, is trying to leverage that in the verification space by auto-generating C-level tests and moving the verification – and design – focus to the creation of well-defined usage scenarios. Read More

December 2, 2013
Electronic Design: Interview: Adnan Hamid Addresses Trends In Chip Verification

Breker is focused 100% on SoC verification. The sophistication of the generated test cases is beyond any other solution in the industry, verifying the SoC more effectively. The Breker approach also is efficient, replacing with automation the dozens or even hundreds of engineers hand-writing verification tests and validation diagnostics. Read More

October 17, 2013
Electronic Engineering Journal: Breker Supplements Simulation

All of these scenarios are now supported by Breker’s TrekSoC-Si product, which complements the existing version. It means that tests generated for simulation can also be applied in all of these other phases of verification and validation.
Read More

September 27, 2013
ESNUG: What were the 3 or 4 most INTERESTING specific tools you saw at DAC this year?

Trek from Breker: Graph-based constraint tool that can help to generate C based tests. Improves verification coverage and catches design bugs in hard-to-hit scenarios. I strongly suggest DV engineers to check out this tool. Read More

August 5, 2013
Electronic Engineering Journal: Software Is in Style: New C-Level SoC Verification Options

Once you move from simulation to emulation or actual silicon, however, the speed of execution is usually much too fast for a testbench to keep up with. Breker says that they have written their own monitor such that the program can write to it at speed and move on; that monitor can then write its data out at whatever speed it needs without slowing down the program. Read More

July 11, 2013
Electronic Engineering Journal: A Tiny Pocket of Space: The Science of a Miniscule Sample

So how in the world do you figure out what to test? Looked at statistically, you need to identify a sample of around 109 points out of 10500 to prove that a design is worthy. To call that a drop in the bucket is like calling the Death Star just a big Sputnik. Where in the heck do you start? Read More

June 12, 2013
Embedded Computing Design: 2013 Top Embedded Innovators: Adnan Hamid, CEO of Breker Verification Systems

Find the best, smartest development teams and work closely with them. We work side by side with people developing the biggest, baddest chips in the world. That’s a lot of fun, but it means that we are constantly being pushed and challenged to evolve our products at a faster pace. We have no choice: We must innovate or die. Read More

June 7, 2013
Electronic Engineering Journal: Amelia Dalton's Weekly Fish Fry Interview with Tom Anderson

We talk about DAC with Tom Anderson (Breker) and ask him about SoC verification and more importantly, what set the Breker booth apart from the rest of the pack on the expo floor this year. Read More

APRIL 13, 2013
McCombs Today: How To Live With An Entrepreneur

"When you are starting a company, there is a lot that needs paying attention to," Adnan says. "She knew business from her family and knew how to handle the bumps and the ups and the downs." Read More

APRIL 12, 2013
EDA DesignLine: What Were they Thinking: Stimulus Coverage

The only way I know how to do this is based on tracking backwards through the design, just like the old tester methods used to do. Those methods proved too compute intensive at the gate level and the patterns generated were too long as design sizes grew and so alternative methods were found, but for functional verification it is what needs to happen. Formal methods attempt to do this as does the graph-based approach being developed by Breker Verification Systems. Read More

MARCH 28, 2013
Chip Design System-Level Design Community: Experts at the Table: Verification Strategies (Part 3)

When it comes to some of these new orthogonal areas like CDC and power, if you get it wrong you're generally dead. With low-power bugs, you basically throw away the chip. If you power down some piece of a chip and it doesn’t come back up, what do you do? Read More

MARCH 8, 2013
Chip Design System-Level Design Community: Experts at the Table: Verification Strategies (Part 2)

There's a lot of trust and a lot of history with companies that have been in the IP business for 15 years. They’ve produced thousands of chips that work. So people are less concerned about re-verification. But the effective re-use of any piece of a verification environment for an IP block is not very well done yet. Read More

FEBRUARY 28, 2013
Chip Design System-Level Design Community: Experts at the Table: Verification Strategies (Part 1)

Because most of the chips out there are SoCs with embedded processors, you need to use the embedded processors to help verify the chip. It's either an automated approach, or just hand-written tests or diagnostics that run simulation/emulation on those embedded processors. The approach is verification from the inside out. Read More

FEBRUARY 27, 2013
Chip Design System-Level Design Community: Verifying Complex Chips

They do need to take advantage of the embedded processors that are within the SoCs to help verify the SoCs from the inside out. After all, if the SoC is doing its job in the final application, it's the embedded processors that are in charge. So it just makes sense to leverage the power of those embedded processors as part of the verification process. Read More

FEBRUARY 22, 2013
Electronic Engineering Times: Anyone for a Free Breakfast Next Week?

I will be moderating a breakfast panel on Tuesday morning 7:00am to 8:15am in the San Carlos/San Juan room at the Doubletree. Its title - How Does Anyone Tape Out Working Chips Anymore? This panel is being organized by Breker Verification, an exhibitor at the conference. Read More

FEBRUARY 20, 2013
Electronic Engineering Times: EDA/IP Weekly Roundup – February 20th 2013

TrekSoC produces multiple streams of real-world user scenarios and schedules the steps so that they cross threads and processors. Since these intertwined test cases are hard to follow, the new GUI features show clearly how the streams are scheduled across threads and how each is making progress in simulation Read More

FEBRUARY 19, 2013
VerificationOnWeb: Dare to Think beyond UVM for SoC Verification

UVM is serving the very purpose it has been developed for – to create interoperable, reusable VIPs. However a full SoC verification is much more than a bunch of VIPs. It requires next abstraction level models such as the graph based scenario models. Such scenario models can then be compiled by TrekSoC to produce C-tests and/or UVM transactions. Read More

FEBRUARY 4, 2013
EDACafe: Breker: Anderson's Verification Tutorial Rocks DesignCon

One of the most widely used low-power design techniques is power shutoff (PSO), a choice that can have the biggest impact on functional verification. Turning off the power completely to unused logic regions called "power domains" saves both dynamic and static leakage power. The outputs of such un-powered domains must be held in isolation from the rest of the chip, and often there is critical state that must be saved and restored. Read More

JANUARY 10, 2013
Electronic Engineering Times: Predictions for 2013 - EDA/IP

A solution known as graph-based scenario models that capture intended behavior of the IP blocks is emerging. 2013 will see broad adoption of this approach, verifying the complete SoC while finally providing a level of verification reuse matching that of design reuse. Read More

JANUARY 9, 2013
Electronic Engineering Times: Stars of DesignCon: Inside-Out Test Verifies Low-Power SoCs

Our new technique uses test cases to verify the SoC from the inside out, rather than from outside-in as with normal test-bench techniques. And when an error is detected, the engineer can step-through the particular failed test case to see where it breaks down. Read More

JANUARY 2, 2013
EDN: A Sneak Peek into DesignCon

Although simple in concept, the verification of SoCs using power shutoff is a significant challenge. This paper looks at a technique that generates self-verifying C test cases that run on the embedded processors in simulation and exercise a wide range of functionality while turning the power domains off and on. Read More

DECEMBER 19, 2012
Electronic Engineering Times: A Look Back on 2012 - Verification

An ongoing trend comes from the consumer electronics market segment driving the creation of SoCs with multiple embedded processors for enhanced product functionality and performance. In 2012, Breker announced support for these types of SoC designs –– a major accomplishment. TrekSoC automatically generates multi-threaded test cases for SoC designs with multiple heterogeneous embedded processors, providing effective verification between stitching and shipping. Read More

DECEMBER 19, 2012
Chip Design System-Level Design Community: Experts at the Table: SoC Verification (Part 3)

In some cases we are taping these things out without fully verifying them, and then we’re taking the hit in the software arena. The problem is functionality and performance over time because of all the bugs in the hardware. All of the big companies are looking at why it takes so long to get the software working. It's because there are bugs in the chip and it takes so long to find them and work around them. Read More

DECEMBER 14, 2012
Chip Design System-Level Design Community: Experts at the Table: SoC Verification (Part 2)

The integration guys have to tape out. They don’t get the opportunity to wait. They know they’re doing a quarter to 10% of the verification they want to do, and where they get hit is in the validation when the chip comes back. The software guys take the hit because the bugs in the chip take a very long time to find and debug—or worse, the chipmaker’s customer finds it, which takes even longer to debug. Read More

DECEMBER 5, 2012
Electronic Engineering Times: A Look Back on 2012: Industry Observations

The biggest surprise of 2012 was the surprise many SoC design teams received when they realized stitch and ship doesn’t work. This optimistic verification process will sink them every time because they’ve failed to exercise a wide range of functional scenarios. A common misperception is that the SoC will work as intended if the IP blocks on the chip have been well verified. In fact, scenarios that represent user applications and measure performance can only be run at the full-chip level. Read More

NOVEMBER 29, 2012
Chip Design System-Level Design Community: Experts at the Table: SoC Verification (Part 1)

We're starting to re-use design components in designs, but we have no idea how to do that for verification or test cases. How do you do plug-and-play verification so you can take information from the IP guy, plug it into an environment that works with the subsystem or system or software and each person along that chain gets to use information from the person downstream from him. This is all about knowledge transfer. Read More

NOVEMBER 28, 2012
Chip Design System-Level Design Community: The Growing Verification Challenge

We are far from being done with demanding more capabilities integrated into smaller chips with more features. The chip doesn't matter, only the product matters, and something only works if it's been tested. Those who can verify will survive; those who can't will die. Read More

November 13, 2012
Electronic Engineering Journal: Breker Tests Multicore

Multicore brings with it a whole slew of new things to go wrong. There may be bus clashes as multiple CPUs decide they’re in charge. You have resource contention and race conditions. There’s cache coherency – a deceptively complex architectural element required only for multicore.
Read More

October 29, 2012
EDA Digest: Evolution and innovation in the EDA ecosystem

There are some very interesting new innovations among the nominations, such as Breker's approach to SoC verification. Read More

SEPTEMBER 12, 2012
Electronic Engineering Times: EDA/IP Weekly Roundup

Breker Verification Systems is on the move and growing its Silicon Valley presence with a new location in San Jose. The office at 1879 Lundy Ave. will accommodate its expanding engineering and customer support teams. Read More

AUGUST 16, 2012
Electronic Engineering Times Europe: Tackling the European Challenges in Verification

Tools such as TrekSoC from Breker Systems automatically generate self-verifying C-based test cases that run on the embedded processors. These test cases exercise the corner cases of the design faster and more thoroughly than hand-written tests and triggers unusual conditions unlikely to occur even by running production code in the processors. Read More

JULY 12, 2012
DowJones VentureWire: Breker Collects $5M to Scale Automated Chip Testing

Breker Verification Systems Inc., a maker of software that automates chip testing, announced it has raised a $5 million Series A round that it plans to use to scale sales, support and research and development. Funding was provided by Astor Capital Group, an Asian private equity fund, Breker said. Financial terms of the round aren't being disclosed, a company spokeswoman said, though they are favorable. Read More

JUNE 8, 2012
Electronic Engineering Journal: Amelia's Weekly Fish Fry Interview with Adnan Hamid

And now, my new hero, the guy who breaks systems: Breker's CEO Adnan Hamid. Adnan and I talk about how he breaks things for a living, the origin of Breker's name, and why Breker decided to move from high-tech hotspot Austin, Texas to Silicon Valley. Read More

JUNE 5, 2012
Electronic Engineering Times: Gary Smith kicks off DAC with his industry commentary

Gary then turned his attention to the intelligent testbench category. He highlighted Breker, who he said was one of many companies in this area several years ago when the category was created. Breker had gone back to the woodshed and emerged with a really good product and had the best technology base out there. Read More

MAY 28, 2012
EDA DesignLine: Enough of the sideshows - it's time for some real advancement in functional verification!

Verification at the SoC level is becoming mandatory, a task beyond the scope of constrained random. I believe that relief is on its way and one solution has been demonstrated to be an effective replacement. While it is not certain that Breker is the company that will ultimately succeed in this market, it's the first to have shown a fully working solution that is being used to verify complex systems. Read More

APRIL 28, 2012
EDACafé: Breker: The Art of Destructive Testing

Here in Silicon Valley, there’s a small company that should be on your radar. Founded in 2003 as a consulting service, the company discovered their solutions – developed to address customers’ verification problems – had become sufficiently robust to be commercialized. Over time, those solutions proved so successful that Breker morphed into a 100-percent product company. Read More

APRIL 9, 2012
Electronic Engineering Journal: Good Pieces Don’t Always Make a Good Whole

Holistic stress testing is what Breker’s TrekSoC tool is about. Given a set of scenarios, the idea is to have the tool automatically create a suite of tests that challenge the corners of operation. The scenarios are where the work is done up front – and this can be done (and is probably best done) long before you approach tape-out. Read More

FEBRUARY 19, 2012
EDACafe: Silicon Valley: EDA Magnet! - Part II

“Previous languages and methodologies have been developed that enable tests to be automatically created from a unified testbench description, but these (previous) approaches don’t scale or adequately address system-level verification. When multiple processors and many different types of IP are involved, methodologies in use for block-level verification break down.” Read More

FEBRUARY 8, 2012
Electronic Engineering Times: EDA/IP Weekly Roundup – Feb 8th

TrekSoC™, the first commercially available software that automates the generation of self-verifying test cases for multi-threaded SoC devices, is in production use at leading semiconductor companies in the U.S., Europe, and India. Read More

FEBRUARY 7, 2012
Electronic Engineering Times: Opinion: The SoC verification market

Unlike transactional testbenches, hand-written embedded-processor tests or other products, TrekSoC combines an intuitive format for describing functionality with powerful engines that generate self-verifying C test cases to verify the specified functionality in existing verification environments. Read More

FEBRUARY 6, 2012
EDACafe: Silicon Valley: EDA Magnet!

Today, Breker considers itself The SoC Verification Company and the first EDA vendor to solve the functional verification challenges of complex SoC designs, something that “no other EDA company is addressing the way Breker is.” Read More

JANUARY 12, 2012
Electronic Engineering Times: Predictions for 2012: Tools

In 2012, there will be much discussion in the industry on a new solution that automates SoC verification so that full system-level verification can be achieved. Read More

OCTOBER 8, 2008
Chip Design: Quality Time?

We need to build coverage around the outcomes you’ve got to test for and the constructs that will give you these applets. Read More

September 11, 2008
Electronic Design: Verification Evolves Into Lean, Mean Bug-Stomping Machines

We see the trend moving back to engineers wanting to make sure they test everything. They’re saying, "I don’t have time to write all the tests so I want a tool to generate the tests." Read More

MARCH 19, 2008
CIMData: IEC Announces 2008 DesignCon Paper Award Winners

2008 Paper Award Winners include the following authors and papers in their respective categories: Adnan Hamid, “Hope Is Not a (Verification) Strategy – Coverage Model Driven Functional Scenario Generation” Read More

FEBRUARY 8, 2008
Chip Design: Nightmares in Functional Verification

What we’re hearing from customers is they want to go with traditional verification at the unit level and at multiple unit levels. But when they get up to the system level, you can’t go with transactional verification. Read More

FEBRUARY 7, 2008
SCDSource: Coverage Metrics Not Enough, Verification Experts Say

Two of the DesignCon panelists represented verification startups that are offering new ideas – Breker Verification Systems and Nusym Technology. Read More

DECEMBER 14, 2007
EDN: EDN Hot 100 Products of 2007

EDN's editors offer up their annual list of the year's 100 most significant ICs, components, buses, boards, EDA tools, power devices, test instruments, and more. Read More

August 2, 2007
Electronic Design: Graph-Based Test-Synthesis Tool Creates Verification Plans

Earlier attempts at graph-based approaches to functional verification haven't panned out, as the graphs proved too large and unwieldy. Breker's tack, which is to combine graph-based techniques with a dependency resolution engine, provides graphical feedback to visualize the verification plan and analyze it for completeness and coverage before beginning simulation runs. Read More

MAY 28, 2007
Electronic Engineering Times: Products Line Up for DAC Debut

What's new: Trek, a graph-based functional test synthesis tool that lets users develop a verification plan, and then automatically generates functional test vectors from it. Read More

MAY 28, 2007
Electronic Engineering Times: Tool Makers Look to Fix Bottlenecks, Fill Gaps

The concept of the "intelligent testbench" will edge a little closer at DAC. Startup Breker Verification Systems, for example, claims its Trek is the first commercial graph-based functional test synthesis tool. Read More

MAY 23, 2007
EDN: EDA Start-Up Breker Has a Plan for Better IC Verification

EDA start-up Breker Verification Systems wants to help you reduce the amount of testbench generation and overall verification you need to do by helping you create a comprehensive IC-verification plan upfront in the functional-verification process and to help you drive better test vectors into your current verification environment. Read More

MAY 14, 2007
Electronic Engineering Times: IC Verification Startup Takes Graphical Approach

At a time when functional verification is consuming much if not most of the IC design cycle, Breker's technology promises to slash the number of personnel required for verification, the amount of verification code and the time required to build a verification environment and start debugging. Read More