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Trek technology will help to achieve a higher level of verification on SoC designs and provide a 2-3X reduction of effort. Olivier Haller
Verification Methodology Manager
ST Microelectronics
We have seen 2x improvements in verification productivity using Trek Jonah Alben
Senior Vice President
NVIDIA Corporation
The engineering team continues to 'Brekerize' the latest design revisions. Terry Hulett
Vice President, Engineering
NetEffect
Their [Breker] SoC verification strategy proposal is solid and we are happy of the improvements it brings to our flow. Design Verification Engineer
Verification Guild/ “Anybody use these tools?”
Trek is reducing development time, improving coverage and easing communication between the various verification stakeholders Olivier Haller
Verification Methodology Manager
ST Microelectronics
I was impressed with how easy it [Trek] was to integrate it into our existing environment. The graph based approach to generating testcases complements our exiting VMM constrained random test-benches very well. Design Verification Engineer
Verification Guild/ “Anybody use these tools?”
[We] are now using Trek in key areas of future GPU projects Jonah Alben
Senior Vice President
NVIDIA Corporation
They [Breker] leverage an already existing testsuite to create more stressful SoC tests Design Verification Engineer
Verification Guild/ “Anybody use these tools?”
Trek is so verstile, that I was able to plug in a Trek graph that modeled the DUT in place of the DUT (whose RTL for some features wasn't ready) allowing me to develop trek graphs that would test features that weren't even implemented yet. Design Verification Engineer Verification Guild/ “Anybody use these tools?”
In both the SystemC and RTL verification efforts, Breker's Trek product was able to help us find deep state functional bugs quickly and efficiently Terry Hulett
Vice President, Engineering
NetEffect
Trek has a natural way of implementing a test environment with knowledge-driven approach of directed tests and the flexibility of incorporating randomness into the scenario generation and checking Design Verification Engineer
Verification Guild/ “Anybody use these tools?”
Constraint solving is really nice when it works. It's a declarative approach that lets you worry about the what, not the how. Trek uses an more imperative approach: you define a graph structure to be traversed. For trivial scenarios this is less elegant than a set of constraints; but as things become more complex you don't hit the performance cliff of constraint solving. David Whipp, NVIDIA Corp.
Verification Guild/ “Anybody use these tools?”
With Breker, we can provide a higher level of verification efficiency with improved coverage closure in pre-silicon and post-silicon verification activities for our customers. François Cerisier
IC Verification Expert
EASii IC
Viewing the coverage capability of the graph was very effective in visualizing what had and had not been verified (helping answer the question ‘Are we done yet?’). Design Verification Engineer
Verification Guild/ “Anybody use these tools?”
Trek is more effective on complex designs. It really helps get to deep corner cases that aren't easily hit. Design Verification Engineer
Verification Guild/ “Anybody use these tools?”
My first impression was to use Trek simply as a testcase creation engine but slowly I'm getting convinced it is useful as "checker" as well - especially the end-to-end checks. Design Verification Engineer
Verification Guild/ “Strategy for System-on-Chip Verification”
Breker System's Trek tool has been refreshing. A new look at how to do functional verification. As a verification engineer, we all look at outcomes to figure out our testplan. Breker takes that to a new level where we can create graphs based on outcomes and even more power comes when one can apply a static analysis to see if all outcomes can really be reached by what was created. Verification Engineer
DeepChip
The one that sticks out for me was Breker Trek. I've been keeping an eye on their development of the tool for a while, and saw a demo. I like that it translates from our feature-based verification planning to what looks like straightforward coding of graphs to randomly verify. Design Verification Engineer
DeepChip/DAC 10
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