TechnologyBreker's Trek family of products and apps automatically generates multi-threaded test cases that verify your chip design more quickly and more thoroughly. These test cases are portable from IP to full-chip level, and from simulation to silicon. Your verification engineers, embedded programmers, and bring-up team no longer have to hand-write throw-away tests, freeing them for revenue-generating tasks.
- TrekUVM enhances transactional Universal Verification Methodology (UVM) testbenches for your networking, processor, and GPU chips.
- TrekSoC links UVM testbenches to generated C test cases running in simulation or acceleration on multiple heterogeneous embedded processors within your system-on-chip (SoC).
- From the same inputs, TrekSoC-Si generates test cases that run on in-circuit emulation (ICE), FPGA prototypes, and actual silicon in your lab.
- Our Cache Coherency TrekApp is a stand-alone turnkey solution for cache coherency verification from simulation to silicon.
July 15, 2015The Breker Trekker: Guest Post: Rain or Shine for the EDA Cloud?... Read More
July 7, 2015The Breker Trekker: Some Fond Memories of EDA Analyst Gary Smith... Read More
June 30, 2015Electronic Engineering Times: Selecting Your M&A Banker... Read More
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September 10-11, 2015
Exclusive technical white papers are available from Breker on topics including cache coherency verification, post-silicon SoC validation, and verification with graph-based scenario models.