TechnologyBreker's Trek family of products and apps automatically generates multi-threaded test cases that verify your chip design more quickly and more thoroughly. These test cases are portable from IP to full-chip level, and from simulation to silicon. Your verification engineers, embedded programmers, and bring-up team no longer have to hand-write throw-away tests, freeing them for revenue-generating tasks.
- TrekUVM enhances transactional Universal Verification Methodology (UVM) testbenches for your networking, processor, and GPU chips.
- TrekSoC links UVM testbenches to generated C test cases running in simulation or acceleration on multiple heterogeneous embedded processors within your system-on-chip (SoC).
- From the same inputs, TrekSoC-Si generates test cases that run on in-circuit emulation (ICE), FPGA prototypes, and actual silicon in your lab.
- Our Cache Coherency TrekApp is a stand-alone turnkey solution for cache coherency verification from simulation to silicon.
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IN THE NEWS"Many aspects of [UVM] are seriously flawed in my opinion and I am glad that it will likely soon die with scenario based generation beginning to get serious attention. Today it is being touted as system verification only, but once it has become even half baked, I believe it will show its superiority and will supplant UVM - even for block level verification." - Brian Bailey READ MORE
Exclusive technical white papers are available from Breker on topics including cache coherency verification, post-silicon SoC validation, and verification with graph-based scenario models.